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28808d20e9
Also add offsets into the IDE parameter block so that it is humanly possible to match the structure to the manufacturer's documentation. (basically this is just changes to comments)
328 lines
12 KiB
C
328 lines
12 KiB
C
/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)wdreg.h 7.1 (Berkeley) 5/9/91
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* $Id: wdreg.h,v 1.26 1999/04/13 20:22:32 peter Exp $
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*/
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/*
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* modified for PC9801 by F.Ukai
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* Kyoto University Microcomputer Club (KMC)
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*/
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/*
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* Disk Controller register definitions.
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*/
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#ifdef PC98
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#define wd_data 0x0 /* data register (R/W - 16 bits) */
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#define wd_error 0x2 /* error register (R) */
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#define wd_precomp wd_error /* write precompensation (W) */
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#define wd_features wd_error /* features register (W) */
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#define wd_seccnt 0x4 /* sector count (R/W) */
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#define wd_sector 0x6 /* first sector number (R/W) */
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#define wd_cyl_lo 0x8 /* cylinder address, low byte (R/W) */
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#define wd_cyl_hi 0xa /* cylinder address, high byte (R/W)*/
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#define wd_sdh 0xc /* sector size/drive/head (R/W)*/
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#define wd_command 0xe /* command register (W) */
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#define wd_status wd_command /* immediate status (R) */
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#define wd_altsts_nec 0x10c /*alternate fixed disk status(via 1015) (R)*/
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#define wd_ctlr_nec 0x10c /*fixed disk controller control(via 1015) (W)*/
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#define wd_altsts_epson 0x3 /*alternate fixed disk status(via 1015) (R)*/
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#define wd_ctlr_epson 0x3 /*fixed disk controller control(via 1015) (W)*/
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#define wd_altsts wd_altsts_nec
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#define WDCTL_4BIT 0x8 /* use four head bits (wd1003) */
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#define WDCTL_RST 0x4 /* reset the controller */
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#define WDCTL_IDS 0x2 /* disable controller interrupts */
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#define wd_digin 0x10e /* disk controller input(via 1015) (R)*/
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#else /* IBM-PC */
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#define wd_data 0x0 /* data register (R/W - 16 bits) */
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#define wd_error 0x1 /* error register (R) */
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#define wd_precomp wd_error /* write precompensation (W) */
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#define wd_features wd_error /* features register (W) */
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#define wd_seccnt 0x2 /* sector count (R/W) */
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#define wd_sector 0x3 /* first sector number (R/W) */
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#define wd_cyl_lo 0x4 /* cylinder address, low byte (R/W) */
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#define wd_cyl_hi 0x5 /* cylinder address, high byte (R/W)*/
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#define wd_sdh 0x6 /* sector size/drive/head (R/W)*/
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#define wd_command 0x7 /* command register (W) */
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#define wd_status wd_command /* immediate status (R) */
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#define wd_altsts 0x206 /*alternate fixed disk status(via 1015) (R)*/
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#define wd_ctlr 0x206 /*fixed disk controller control(via 1015) (W)*/
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#define WDCTL_4BIT 0x8 /* use four head bits (wd1003) */
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#define WDCTL_RST 0x4 /* reset the controller */
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#define WDCTL_IDS 0x2 /* disable controller interrupts */
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#define wd_digin 0x207 /* disk controller input(via 1015) (R)*/
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#endif /* PC98 */
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/*
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* Status Bits.
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*/
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#define WDCS_BUSY 0x80 /* Controller busy bit. */
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#define WDCS_READY 0x40 /* Selected drive is ready */
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#define WDCS_WRTFLT 0x20 /* Write fault */
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#define WDCS_SEEKCMPLT 0x10 /* Seek complete */
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#define WDCS_DRQ 0x08 /* Data request bit. */
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#define WDCS_ECCCOR 0x04 /* ECC correction made in data */
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#define WDCS_INDEX 0x02 /* Index pulse from selected drive */
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#define WDCS_ERR 0x01 /* Error detect bit. */
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#define WDCS_BITS "\020\010busy\007rdy\006wrtflt\005seekdone\004drq\003ecc_cor\002index\001err"
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#define WDERR_ABORT 0x04
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#define WDERR_BITS "\020\010badblk\007uncorr\006id_crc\005no_id\003abort\002tr000\001no_dam"
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/*
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* Commands for Disk Controller.
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*/
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#define WDCC_RESTORE 0x10 /* disk restore code -- resets cntlr */
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#define WDCC_READ 0x20 /* disk read code */
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#define WDCC_WRITE 0x30 /* disk write code */
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#define WDCC__LONG 0x02 /* modifier -- access ecc bytes */
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#define WDCC__NORETRY 0x01 /* modifier -- no retrys */
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#define WDCC_FORMAT 0x50 /* disk format code */
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#define WDCC_DIAGNOSE 0x90 /* controller diagnostic */
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#define WDCC_IDC 0x91 /* initialize drive command */
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#define WDCC_READ_MULTI 0xC4 /* read multiple */
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#define WDCC_WRITE_MULTI 0xC5 /* write multiple */
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#define WDCC_SET_MULTI 0xC6 /* set multiple count */
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#define WDCC_READ_DMA 0xC8 /* read using DMA */
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#define WDCC_WRITE_DMA 0xCA /* write using DMA */
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#define WDCC_EXTDCMD 0xE0 /* send extended command */
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#define WDCC_READP 0xEC /* read parameters from controller */
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#define WDCC_FEATURES 0xEF /* features control */
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#define WDCC_DEFECT 0xF0 /* read defect list */
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#define WDFEA_NORCACHE 0x55 /* read cache disable */
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#define WDFEA_RCACHE 0xAA /* read cache enable */
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#define WDFEA_NOWCACHE 0x82 /* write cache disable */
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#define WDFEA_WCACHE 0x02 /* write cache enable */
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#define WDFEA_SETXFER 0x03 /* set transfer mode */
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#define WD_STEP 0 /* winchester- default 35us step */
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#define WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */
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#define WDSD_LBA 0x40 /* use Logical Block Adressing */
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#ifdef KERNEL
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/*
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* read parameters command returns this:
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*/
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struct wdparams {
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/*
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* XXX partly based on DRAFT X3T13/1153D rev 14.
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* by the time you read this it will have changed.
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* Offsets in words
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* (as that's how they are usually presented in tables
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* e.g. QUANTUM Product manuals)
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*/
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/* drive info */
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short wdp_config; /*0 general configuration bits */
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u_short wdp_cylinders; /*1 number of cylinders */
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short wdp_reserved2; /*2*/
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u_short wdp_heads; /*3 number of heads */
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short wdp_unfbytespertrk; /*4 number of unformatted bytes/track */
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short wdp_unfbytes; /*5 number of unformatted bytes/sec */
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u_short wdp_sectors; /*6 number of sectors per track */
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short wdp_vendorunique[3]; /*7,8,9*/
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/* controller info */
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char wdp_serial[20]; /*10-19 serial number */
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short wdp_buffertype; /*20 buffer type */
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#define WDTYPE_SINGLEPORTSECTOR 1 /* single port, single sector buffer */
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#define WDTYPE_DUALPORTMULTI 2 /* dual port, multiple sector buffer */
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#define WDTYPE_DUALPORTMULTICACHE 3 /* above plus track cache */
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short wdp_buffersize; /*21 buffer size, in 512-byte units */
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short wdp_necc; /*22 ecc bytes appended */
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char wdp_rev[8]; /*23-26 firmware revision */
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char wdp_model[40]; /*27-46 model name */
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char wdp_nsecperint; /*47L sectors per interrupt */
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char wdp_vendorunique1; /*47H*/
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short wdp_usedmovsd; /*48 can use double word read/write? */
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char wdp_vendorunique2; /*49L*/
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char wdp_capability; /*49H various capability bits */
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short wdp_cap_validate; /*50 validation for above */
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char wdp_vendorunique3; /*51L*/
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char wdp_opiomode; /*51H PIO modes 0-2 */
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char wdp_vendorunique4; /*52*/
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char wdp_odmamode; /*52 old DMA modes, not in ATA-3 */
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short wdp_atavalid; /*53 validation for newer fields */
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short wdp_currcyls; /*54 */
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short wdp_currheads; /*55 */
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short wdp_currsectors; /*56 */
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short wdp_currsize0; /*57 CHS size*/
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short wdp_currsize1; /*58 CHS size*/
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char wdp_currmultsect; /*59L */
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char wdp_multsectvalid; /*59H */
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int wdp_lbasize; /*60,61*/
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short wdp_dmasword; /*62 obsolete in ATA-3 */
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short wdp_dmamword; /*63 multiword DMA modes */
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short wdp_eidepiomodes; /*64 advanced PIO modes */
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short wdp_eidedmamin; /*65 fastest possible DMA timing */
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short wdp_eidedmanorm; /*66 recommended DMA timing */
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short wdp_eidepioblind; /*67 fastest possible blind PIO */
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short wdp_eidepioacked; /*68 fastest possible IORDY PIO */
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short wdp_reserved69; /*69*/
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short wdp_reserved70; /*70*/
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short wdp_reserved71; /*71*/
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short wdp_reserved72; /*72*/
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short wdp_reserved73; /*73*/
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short wdp_reserved74; /*74*/
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short wdp_queuelen; /*75*/
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short wdp_reserved76; /*76*/
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short wdp_reserved77; /*77*/
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short wdp_reserved78; /*78*/
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short wdp_reserved79; /*79*/
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short wdp_versmaj; /*80*/
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short wdp_versmin; /*81*/
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short wdp_featsupp1; /*82*/
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short wdp_featsupp2; /*83*/
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short wdp_featsupp3; /*84*/
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short wdp_featenab1; /*85*/
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short wdp_featenab2; /*86*/
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short wdp_featenab3; /*87*/
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short wdp_udmamode; /*88 UltraDMA modes */
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short wdp_erasetime; /*89*/
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short wdp_enherasetime; /*90*/
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short wdp_apmlevel; /*91*/
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short wdp_reserved92[34]; /*92*/
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short wdp_rmvcap; /*93*/
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short wdp_securelevel; /*94*/
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};
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/*
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* wd driver entry points
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*/
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#ifdef B_FORMAT
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int wdformat(struct buf *bp);
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#endif
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/*
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* IDE DMA support.
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* This is based on what is needed for the IDE DMA function of the Intel
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* Triton chipset; hopefully it's general enough to be used for other
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* chipsets as well.
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*
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* To use this:
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* For each drive which you might want to do DMA on, call wdd_candma()
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* to get a cookie. If it returns a null pointer, then the drive
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* can't do DMA. Then call wdd_dmainit() to initialize the controller
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* and drive. wdd_dmainit should leave PIO modes operational, though
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* perhaps with suboptimal performance.
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*
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* Check the transfer by calling wdd_dmaverify(). The cookie is what
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* you got before; vaddr is the virtual address of the buffer to be
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* written; len is the length of the buffer; and direction is either
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* B_READ or B_WRITE. This function verifies that the DMA hardware is
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* capable of handling the request you've made.
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*
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* Setup the transfer by calling wdd_dmaprep(). This takes the same
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* paramaters as wdd_dmaverify().
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*
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* Send a read/write DMA command to the drive.
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*
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* Call wdd_dmastart().
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*
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* Wait for an interrupt. Multi-sector transfers will only interrupt
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* at the end of the transfer.
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*
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* Call wdd_dmadone(). It will return the status as defined by the
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* WDDS_* constants below.
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*/
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struct wddma {
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void *(*wdd_candma) /* returns a cookie if PCI */
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__P((int iobase_wd, int ctlr, int unit));
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int (*wdd_dmaverify) /* verify that request is DMA-able */
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__P((void *cookie, char *vaddr, u_long len, int direction));
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int (*wdd_dmaprep) /* prepare DMA hardware */
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__P((void *cookie, char *vaddr, u_long len, int direction));
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void (*wdd_dmastart) /* begin DMA transfer */
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__P((void *cookie));
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int (*wdd_dmadone) /* DMA transfer completed */
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__P((void *cookie));
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int (*wdd_dmastatus) /* return status of DMA */
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__P((void *cookie));
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int (*wdd_dmainit) /* initialize controller and drive */
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__P((void *cookie,
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struct wdparams *wp,
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int(wdcmd)__P((int mode, void *wdinfo)),
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void *wdinfo));
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int (*wdd_iobase) /* returns iobase address */
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__P((void *cookie));
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int (*wdd_altiobase) /* returns altiobase address */
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__P((void *cookie));
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};
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/* logical status bits returned by wdd_dmastatus */
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#define WDDS_ACTIVE 0x0001
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#define WDDS_ERROR 0x0002
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#define WDDS_INTERRUPT 0x0004
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#define WDDS_BITS "\20\4interrupt\2error\1active"
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/* defines for ATA timing modes */
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#define WDDMA_GRPMASK 0xf8
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#define WDDMA_MODEMASK 0x07
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/* flow-controlled PIO modes */
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#define WDDMA_PIO 0x10
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#define WDDMA_PIO3 0x10
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#define WDDMA_PIO4 0x11
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/* multi-word DMA timing modes */
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#define WDDMA_MDMA 0x20
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#define WDDMA_MDMA0 0x20
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#define WDDMA_MDMA1 0x21
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#define WDDMA_MDMA2 0x22
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/* Ultra DMA timing modes */
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#define WDDMA_UDMA 0x40
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#define WDDMA_UDMA0 0x40
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#define WDDMA_UDMA1 0x41
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#define WDDMA_UDMA2 0x42
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#define Q_CMD640B 0x00000001 /* CMD640B quirk: serialize IDE channels */
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void wdc_pci(int quirks);
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extern struct wddma wddma[];
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void wdintr __P((void *unit));
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#endif /* KERNEL */
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