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4d9ac6c76f
level. The distinction was artificial. Some more movement around the deck charis is likely depending on the fallout from this one. Paths were corrected after the svn mv. Hope that's OK.
295 lines
9.7 KiB
C
295 lines
9.7 KiB
C
/* $NetBSD: adm5120reg.h,v 1.1 2007/03/20 08:52:03 dyoung Exp $ */
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/*-
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* Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. The names of the authors may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _ADM5120REG_H_
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#define _ADM5120REG_H_
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/* Helpers from NetBSD */
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/* __BIT(n): nth bit, where __BIT(0) == 0x1. */
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#define __BIT(__n) \
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(((__n) >= NBBY * sizeof(uintmax_t)) ? 0 : ((uintmax_t)1 << (__n)))
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/* __BITS(m, n): bits m through n, m < n. */
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#define __BITS(__m, __n) \
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((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1))
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/* Last byte of physical address space. */
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#define ADM5120_TOP 0x1fffffff
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#define ADM5120_BOTTOM 0x0
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/* Flash addresses */
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#define ADM5120_BASE_SRAM0 0x1fc00000
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/* UARTs */
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#define ADM5120_BASE_UART1 0x12800000
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#define ADM5120_BASE_UART0 0x12600000
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/* ICU */
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#define ADM5120_BASE_ICU 0x12200000
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#define ICU_STATUS_REG 0x00
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#define ICU_RAW_STATUS_REG 0x04
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#define ICU_ENABLE_REG 0x08
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#define ICU_DISABLE_REG 0x0c
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#define ICU_SOFT_REG 0x10
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#define ICU_MODE_REG 0x14
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#define ICU_FIQ_STATUS_REG 0x18
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#define ICU_TESTSRC_REG 0x1c
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#define ICU_SRCSEL_REG 0x20
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#define ICU_LEVEL_REG 0x24
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#define ICU_INT_MASK 0x3ff
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/* Switch */
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#define ADM5120_BASE_SWITCH 0x12000000
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#define SW_CODE_REG 0x00
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#define CLKS_MASK 0x00300000
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#define CLKS_175MHZ 0x00000000
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#define CLKS_200MHZ 0x00100000
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#define SW_SFTRES_REG 0x04
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#define SW_MEMCONT_REG 0x1c
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#define SDRAM_SIZE_4MBYTES 0x0001
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#define SDRAM_SIZE_8MBYTES 0x0002
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#define SDRAM_SIZE_16MBYTES 0x0003
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#define SDRAM_SIZE_64MBYTES 0x0004
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#define SDRAM_SIZE_128MBYTES 0x0005
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#define SDRAM_SIZE_MASK 0x0007
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#define SRAM0_SIZE_SHIFT 8
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#define SRAM1_SIZE_SHIFT 16
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#define SRAM_MASK 0x0007
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#define SRAM_SSIZE 0x40000
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#define ADM5120_BASE_PCI_CONFDATA 0x115ffff8
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#define ADM5120_BASE_PCI_CONFADDR 0x115ffff0
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#define ADM5120_BASE_PCI_IO 0x11500000
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#define ADM5120_BASE_PCI_MEM 0x11400000
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#define ADM5120_BASE_USB 0x11200000
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#define ADM5120_BASE_MPMC 0x11000000
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#define ADM5120_BASE_EXTIO1 0x10e00000
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#define ADM5120_BASE_EXTIO0 0x10c00000
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#define ADM5120_BASE_RSVD0 0x10800000
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#define ADM5120_BASE_SRAM1 0x10000000
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#define _REG_READ(b, o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((b) + (o)))
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#define SW_READ(o) _REG_READ(ADM5120_BASE_SWITCH, o)
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#define _REG_WRITE(b, o, v) (_REG_READ(b, o)) = (v)
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#define SW_WRITE(o, v) _REG_WRITE(ADM5120_BASE_SWITCH,o, v)
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/* USB */
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/* Watchdog Timers: base address is switch controller */
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#define ADM5120_WDOG0 0x00c0
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#define ADM5120_WDOG1 0x00c4
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#define ADM5120_WDOG0_WTTR __BIT(31) /* 0: do not reset,
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* 1: reset on wdog expiration
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*/
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#define ADM5120_WDOG1_WDE __BIT(31) /* 0: deactivate,
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* 1: drop all CPU-bound
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* packets, disable flow
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* control on all ports.
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*/
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#define ADM5120_WDOG_WTS_MASK __BITS(30, 16) /* Watchdog Timer Set:
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* timer expires when it
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* reaches WTS. Units of
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* 10ms.
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*/
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#define ADM5120_WDOG_RSVD __BIT(15)
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#define ADM5120_WDOG_WT_MASK __BITS(14, 0) /* Watchdog Timer:
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* counts up, write to clear.
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*/
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/* GPIO: base address is switch controller */
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#define ADM5120_GPIO0 0x00b8
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#define ADM5120_GPIO0_OV __BITS(31, 24) /* rw: output value */
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#define ADM5120_GPIO0_OE __BITS(23, 16) /* rw: output enable,
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* bit[n] = 0 -> input
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* bit[n] = 1 -> output
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*/
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#define ADM5120_GPIO0_IV __BITS(15, 8) /* ro: input value */
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#define ADM5120_GPIO0_RSVD __BITS(7, 0) /* rw: reserved */
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#define ADM5120_GPIO2 0x00bc
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#define ADM5120_GPIO2_EW __BIT(6) /* 1: enable wait state pin,
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* pin GPIO[0], for GPIO[1]
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* or GPIO[3] Chip Select:
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* memory controller waits for
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* WAIT# inactive (high).
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*/
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#define ADM5120_GPIO2_CSX1 __BIT(5) /* 1: GPIO[3:4] act as
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* Chip Select for
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* External I/O 1 (CSX1)
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* and External Interrupt 1
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* (INTX1), respectively.
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* 0: CSX1/INTX1 disabled
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*/
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#define ADM5120_GPIO2_CSX0 __BIT(4) /* 1: GPIO[1:2] act as
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* Chip Select for
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* External I/O 0 (CSX0)
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* and External Interrupt 0
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* (INTX0), respectively.
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* 0: CSX0/INTX0 disabled
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*/
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/* MultiPort Memory Controller (MPMC) */
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#define ADM5120_MPMC_CONTROL 0x000
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#define ADM5120_MPMC_CONTROL_DWB __BIT(3) /* write 1 to
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* drain write
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* buffers. write 0
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* for normal buffer
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* operation.
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*/
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#define ADM5120_MPMC_CONTROL_LPM __BIT(2) /* 1: activate low-power
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* mode. SDRAM is
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* still refreshed.
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*/
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#define ADM5120_MPMC_CONTROL_AM __BIT(1) /* 1: address mirror:
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* static memory
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* chip select 0
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* is mapped to chip
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* select 1.
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*/
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#define ADM5120_MPMC_CONTROL_ME __BIT(0) /* 0: disable MPMC.
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* DRAM is not
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* refreshed.
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* 1: enable MPMC.
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*/
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#define ADM5120_MPMC_STATUS 0x004
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#define ADM5120_MPMC_STATUS_SRA __BIT(2) /* read-only
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* MPMC operating mode
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* indication,
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* 1: self-refresh
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* acknowledge
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* 0: normal mode
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*/
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#define ADM5120_MPMC_STATUS_WBS __BIT(1) /* read-only
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* write-buffer status,
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* 0: buffers empty
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* 1: contain data
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*/
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#define ADM5120_MPMC_STATUS_BU __BIT(0) /* read-only MPMC
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* "busy" indication,
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* 0: MPMC idle
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* 1: MPMC is performing
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* memory transactions
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*/
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#define ADM5120_MPMC_SEW 0x080
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#define ADM5120_MPMC_SEW_RSVD __BITS(31, 10)
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#define ADM5120_MPMC_SEW_EWTO __BITS(9, 0) /* timeout access after
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* 16 * (n + 1) clock cycles
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* (XXX which clock?)
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*/
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#define ADM5120_MPMC_SC(__i) (0x200 + 0x020 * (__i))
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#define ADM5120_MPMC_SC_RSVD0 __BITS(31, 21)
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#define ADM5120_MPMC_SC_WP __BIT(20) /* 1: write protect */
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#define ADM5120_MPMC_SC_BE __BIT(20) /* 1: enable write buffer */
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#define ADM5120_MPMC_SC_RSVD1 __BITS(18, 9)
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#define ADM5120_MPMC_SC_EW __BIT(8) /* 1: enable extended wait;
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*/
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#define ADM5120_MPMC_SC_BLS __BIT(7) /* 0: byte line state pins
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* are active high on read,
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* active low on write.
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*
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* 1: byte line state pins
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* are active low on read and
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* on write.
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*/
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#define ADM5120_MPMC_SC_CCP __BIT(6) /* 0: chip select is active low,
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* 1: active high
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*/
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#define ADM5120_MPMC_SC_RSVD2 __BITS(5, 4)
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#define ADM5120_MPMC_SC_PM __BIT(3) /* 0: page mode disabled,
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* 1: enable asynchronous
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* page mode four
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*/
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#define ADM5120_MPMC_SC_RSVD3 __BIT(2)
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#define ADM5120_MPMC_SC_MW_MASK __BITS(1, 0) /* memory width, bits */
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#define ADM5120_MPMC_SC_MW_8B __SHIFTIN(0, ADM5120_MPMC_SC_MW_MASK)
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#define ADM5120_MPMC_SC_MW_16B __SHIFTIN(1, ADM5120_MPMC_SC_MW_MASK)
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#define ADM5120_MPMC_SC_MW_32B __SHIFTIN(2, ADM5120_MPMC_SC_MW_MASK)
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#define ADM5120_MPMC_SC_MW_RSVD __SHIFTIN(3, ADM5120_MPMC_SC_MW_MASK)
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#define ADM5120_MPMC_SWW(__i) (0x204 + 0x020 * (__i))
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#define ADM5120_MPMC_SWW_RSVD __BITS(31, 4)
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#define ADM5120_MPMC_SWW_WWE __BITS(3, 0) /* delay (n + 1) * HCLK cycles
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* after asserting chip select
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* (CS) before asserting write
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* enable (WE)
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*/
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#define ADM5120_MPMC_SWO(__i) (0x208 + 0x020 * (__i))
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#define ADM5120_MPMC_SWO_RSVD __BITS(31, 4)
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#define ADM5120_MPMC_SWO_WOE __BITS(3, 0) /* delay n * HCLK cycles
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* after asserting chip select
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* before asserting output
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* enable (OE)
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*/
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#define ADM5120_MPMC_SWR(__i) (0x20c + 0x020 * (__i))
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#define ADM5120_MPMC_SWR_RSVD __BITS(31, 5)
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#define ADM5120_MPMC_SWR_NMRW __BITS(4, 0) /* read wait states for
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* either first page-mode
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* access or for non-page mode
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* read, (n + 1) * HCLK cycles
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*/
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#define ADM5120_MPMC_SWP(__i) (0x210 + 0x020 * (__i))
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#define ADM5120_MPMC_SWP_RSVD __BITS(31, 5)
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#define ADM5120_MPMC_SWP_WPS __BITS(4, 0) /* read wait states for
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* second and subsequent
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* page-mode read,
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* (n + 1) * HCLK cycles
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*/
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#define ADM5120_MPMC_SWWR(__i) (0x214 + 0x020 * (__i))
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#define ADM5120_MPMC_SWWR_RSVD __BITS(31, 5)
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#define ADM5120_MPMC_SWWR_WWS __BITS(4, 0) /* write wait states after
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* the first read (??),
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* (n + 2) * HCLK cycles
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*/
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#define ADM5120_MPMC_SWT(__i) (0x218 + 0x020 * (__i))
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#define ADM5120_MPMC_SWT_RSVD __BITS(31, 4)
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#define ADM5120_MPMC_SWT_WAITTURN __BITS(3, 0) /* bus turnaround time,
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* (n + 1) * HCLK cycles
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*/
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#endif /* _ADM5120REG_H_ */
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