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86be9f0dd5
1.3 of Intelб╝ Virtualization Technology for Directed I/O Architecture Specification. The Extended Context and PASIDs from the rev. 2.2 are not supported, but I am not aware of any released hardware which implements them. Code does not use queued invalidation, see comments for the reason, and does not provide interrupt remapping services. Code implements the management of the guest address space per domain and allows to establish and tear down arbitrary mappings, but not partial unmapping. The superpages are created as needed, but not promoted. Faults are recorded, fault records could be obtained programmatically, and printed on the console. Implement the busdma(9) using DMARs. This busdma backend avoids bouncing and provides security against misbehaving hardware and driver bad programming, preventing leaks and corruption of the memory by wild DMA accesses. By default, the implementation is compiled into amd64 GENERIC kernel but disabled; to enable, set hw.dmar.enable=1 loader tunable. Code is written to work on i386, but testing there was low priority, and driver is not enabled in GENERIC. Even with the DMAR turned on, individual devices could be directed to use the bounce busdma with the hw.busdma.pci<domain>:<bus>:<device>:<function>.bounce=1 tunable. If DMARs are capable of the pass-through translations, it is used, otherwise, an identity-mapping page table is constructed. The driver was tested on Xeon 5400/5500 chipset legacy machine, Haswell desktop and E5 SandyBridge dual-socket boxes, with ahci(4), ata(4), bce(4), ehci(4), mfi(4), uhci(4), xhci(4) devices. It also works with em(4) and igb(4), but there some fixes are needed for drivers, which are not committed yet. Intel GPUs do not work with DMAR (yet). Many thanks to John Baldwin, who explained me the newbus integration; Peter Holm, who did all testing and helped me to discover and understand several incredible bugs; and to Jim Harris for the access to the EDS and BWG and for listening when I have to explain my findings to somebody. Sponsored by: The FreeBSD Foundation MFC after: 1 month
196 lines
5.4 KiB
C
196 lines
5.4 KiB
C
/*-
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* Copyright (c) 2013 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Konstantin Belousov <kib@FreeBSD.org>
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* under sponsorship from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/memdesc.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/rwlock.h>
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#include <sys/smp.h>
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#include <sys/taskqueue.h>
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#include <sys/tree.h>
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#include <machine/bus.h>
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#include <contrib/dev/acpica/include/acpi.h>
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#include <contrib/dev/acpica/include/accommon.h>
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#include <dev/acpica/acpivar.h>
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#include <vm/vm.h>
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#include <vm/vm_extern.h>
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#include <vm/vm_kern.h>
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#include <vm/vm_object.h>
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#include <vm/vm_page.h>
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#include <vm/vm_pager.h>
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#include <vm/vm_map.h>
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#include <x86/include/busdma_impl.h>
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#include <x86/iommu/intel_reg.h>
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#include <x86/iommu/busdma_dmar.h>
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#include <x86/iommu/intel_dmar.h>
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#include <dev/pci/pcivar.h>
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typedef void (*dmar_quirk_fun)(struct dmar_unit *);
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struct intel_dmar_quirk_cpu {
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u_int ext_family;
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u_int ext_model;
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u_int family_code;
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u_int model;
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u_int stepping;
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dmar_quirk_fun quirk;
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const char *descr;
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};
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struct intel_dmar_quirk_nb {
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u_int dev_id;
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u_int rev_no;
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dmar_quirk_fun quirk;
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const char *descr;
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};
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static void
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dmar_match_quirks(struct dmar_unit *dmar,
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const struct intel_dmar_quirk_nb *nb_quirks, int nb_quirks_len,
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const struct intel_dmar_quirk_cpu *cpu_quirks, int cpu_quirks_len)
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{
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device_t nb;
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const struct intel_dmar_quirk_nb *nb_quirk;
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const struct intel_dmar_quirk_cpu *cpu_quirk;
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u_int p[4];
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u_int dev_id, rev_no;
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u_int ext_family, ext_model, family_code, model, stepping;
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int i;
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if (nb_quirks != NULL) {
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nb = pci_find_bsf(0, 0, 0);
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if (nb != NULL) {
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dev_id = pci_get_device(nb);
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rev_no = pci_get_revid(nb);
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for (i = 0; i < nb_quirks_len; i++) {
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nb_quirk = &nb_quirks[i];
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if (nb_quirk->dev_id == dev_id &&
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nb_quirk->rev_no == rev_no) {
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if (bootverbose) {
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device_printf(dmar->dev,
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"NB IOMMU quirk %s\n",
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nb_quirk->descr);
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}
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nb_quirk->quirk(dmar);
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}
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}
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} else {
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device_printf(dmar->dev, "cannot find northbridge\n");
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}
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}
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if (cpu_quirks != NULL) {
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do_cpuid(1, p);
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ext_family = (p[0] & CPUID_EXT_FAMILY) >> 20;
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ext_model = (p[0] & CPUID_EXT_MODEL) >> 16;
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family_code = (p[0] & CPUID_FAMILY) >> 8;
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model = (p[0] & CPUID_MODEL) >> 4;
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stepping = p[0] & CPUID_STEPPING;
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for (i = 0; i < cpu_quirks_len; i++) {
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cpu_quirk = &cpu_quirks[i];
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if (cpu_quirk->ext_family == ext_family &&
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cpu_quirk->ext_model == ext_model &&
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cpu_quirk->family_code == family_code &&
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cpu_quirk->model == model &&
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(cpu_quirk->stepping == -1 ||
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cpu_quirk->stepping == stepping)) {
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if (bootverbose) {
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device_printf(dmar->dev,
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"CPU IOMMU quirk %s\n",
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cpu_quirk->descr);
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}
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cpu_quirk->quirk(dmar);
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}
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}
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}
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}
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static void
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nb_5400_no_low_high_prot_mem(struct dmar_unit *unit)
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{
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unit->hw_cap &= ~(DMAR_CAP_PHMR | DMAR_CAP_PLMR);
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}
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static const struct intel_dmar_quirk_nb pre_use_nb[] = {
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{
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.dev_id = 0x4001, .rev_no = 0x20,
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.quirk = nb_5400_no_low_high_prot_mem,
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.descr = "5400 E23" /* no low/high protected memory */
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},
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{
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.dev_id = 0x4003, .rev_no = 0x20,
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.quirk = nb_5400_no_low_high_prot_mem,
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.descr = "5400 E23" /* no low/high protected memory */
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},
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};
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static void
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cpu_e5_am9(struct dmar_unit *unit)
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{
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unit->hw_cap &= ~(0x3fULL << 48);
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unit->hw_cap |= (9ULL << 48);
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}
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static const struct intel_dmar_quirk_cpu post_ident_cpu[] = {
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{
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.ext_family = 0, .ext_model = 2, .family_code = 6, .model = 13,
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.stepping = 6, .quirk = cpu_e5_am9,
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.descr = "E5 BT176" /* AM should be at most 9 */
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},
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};
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void
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dmar_quirks_pre_use(struct dmar_unit *dmar)
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{
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if (!dmar_barrier_enter(dmar, DMAR_BARRIER_USEQ))
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return;
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DMAR_LOCK(dmar);
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dmar_match_quirks(dmar, pre_use_nb, nitems(pre_use_nb),
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NULL, 0);
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dmar_barrier_exit(dmar, DMAR_BARRIER_USEQ);
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}
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void
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dmar_quirks_post_ident(struct dmar_unit *dmar)
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{
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dmar_match_quirks(dmar, NULL, 0, post_ident_cpu,
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nitems(post_ident_cpu));
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}
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