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389 lines
16 KiB
C
389 lines
16 KiB
C
/*
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* Copyright (c) 2004-2005 HighPoint Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _ATAPI_H_
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#define _ATAPI_H_
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#pragma pack(1)
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/***************************************************************************
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* IDE IO Register File
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***************************************************************************/
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/*
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* IDE IO Port definition
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*/
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typedef struct _IDE_REGISTERS_1 {
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USHORT Data; /* RW: Data port feature register */
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UCHAR BlockCount; /* RW: Sector count */
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UCHAR BlockNumber; /* RW: Sector number & LBA 0-7 */
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UCHAR CylinderLow; /* RW: Cylinder low & LBA 8-15 */
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UCHAR CylinderHigh; /* RW: Cylinder hign & LBA 16-23 */
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UCHAR DriveSelect; /* RW: Drive/head & LBA 24-27 */
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UCHAR Command; /* RO: Status WR:Command */
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} IDE_REGISTERS_1, *PIDE_REGISTERS_1;
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/*
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* IDE status definitions
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*/
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#define IDE_STATUS_ERROR 0x01 /* Error Occurred in Execution */
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#define IDE_STATUS_INDEX 0x02 /* is vendor specific */
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#define IDE_STATUS_CORRECTED_ERROR 0x04 /* Corrected Data */
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#define IDE_STATUS_DRQ 0x08 /* Ready to transfer data */
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#define IDE_STATUS_DSC 0x10 /* not defined in ATA-2 */
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#define IDE_STATUS_DWF 0x20 /* Device Fault has been detected */
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#define IDE_STATUS_DRDY 0x40 /* Device Ready to accept command */
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#define IDE_STATUS_IDLE 0x50 /* Device is OK */
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#define IDE_STATUS_BUSY 0x80 /* Device Busy, must wait */
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#define IDE_ERROR_BAD_BLOCK 0x80 /* Reserved now */
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#define IDE_ERROR_DATA_ERROR 0x40 /* Uncorreectable Data Error */
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#define IDE_ERROR_MEDIA_CHANGE 0x20 /* Media Changed */
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#define IDE_ERROR_ID_NOT_FOUND 0x10 /* ID Not Found */
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#define IDE_ERROR_MEDIA_CHANGE_REQ 0x08 /* Media Change Requested */
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#define IDE_ERROR_COMMAND_ABORTED 0x04 /* Aborted Command */
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#define IDE_ERROR_TRACK0_NOT_FOUND 0x02 /* Track 0 Not Found */
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#define IDE_ERROR_ADDRESS_NOT_FOUND 0x01 /* Address Mark Not Found */
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#define LBA_MODE 0x40
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/*
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* IDE command definitions
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*/
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#define IDE_COMMAND_RECALIBRATE 0x10 /* Recalibrate */
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#define IDE_COMMAND_READ 0x20 /* Read Sectors with retry */
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#define IDE_COMMAND_WRITE 0x30 /* Write Sectors with retry */
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#define IDE_COMMAND_VERIFY 0x40 /* Read Verify Sectors with Retry */
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#define IDE_COMMAND_SEEK 0x70 /* Seek */
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#define IDE_COMMAND_SET_DRIVE_PARAMETER 0x91 /* Initialize Device Parmeters */
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#define IDE_COMMAND_GET_MEDIA_STATUS 0xDA
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#define IDE_COMMAND_DOOR_LOCK 0xDE /* Door Lock */
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#define IDE_COMMAND_DOOR_UNLOCK 0xDF /* Door Unlock */
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#define IDE_COMMAND_ENABLE_MEDIA_STATUS 0xEF /* Set Features */
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#define IDE_COMMAND_IDENTIFY 0xEC /* Identify Device */
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#define IDE_COMMAND_MEDIA_EJECT 0xED
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#define IDE_COMMAND_SET_FEATURES 0xEF /* IDE set features command */
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#define IDE_COMMAND_FLUSH_CACHE 0xE7
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#define IDE_COMMAND_STANDBY_IMMEDIATE 0xE0
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#ifndef NOT_SUPPORT_MULTIPLE
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#define IDE_COMMAND_READ_MULTIPLE 0xC4 /* Read Multiple */
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#define IDE_COMMAND_WRITE_MULTIPLE 0xC5 /* Write Multiple */
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#define IDE_COMMAND_SET_MULTIPLE 0xC6 /* Set Multiple Mode */
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#endif
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#ifndef NOT_SUPPORT_DMA
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#define IDE_COMMAND_DMA_READ 0xc8 /* IDE DMA read command */
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#define IDE_COMMAND_DMA_WRITE 0xca /* IDE DMA write command */
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#endif
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#define IDE_COMMAND_READ_DMA_QUEUE 0xc7 /* IDE read DMA queue command */
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#define IDE_COMMAND_WRITE_DMA_QUEUE 0xcc /* IDE write DMA queue command */
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#define IDE_COMMAND_SERVICE 0xA2 /* IDE service command command */
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#define IDE_COMMAND_NOP 0x00 /* IDE NOP command */
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#define IDE_STATUS_SRV 0x10
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#define IDE_RELEASE_BUS 4
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/*#define IDE_COMMAND_FLUSH_CACHE_EXT */
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#define IDE_COMMAND_READ_DMA_EXT 0x25
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#define IDE_COMMAND_READ_QUEUE_EXT 0x26
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#define IDE_COMMAND_READ_MULTIPLE_EXT 0x29
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#define IDE_COMMAND_READ_MAX_ADDR 0x27
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#define IDE_COMMAND_READ_EXT 0x24
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#define IDE_COMMAND_VERIFY_EXT 0x42
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#define IDE_COMMAND_SET_MULTIPLE_EXT 0x37
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#define IDE_COMMAND_WRITE_DMA_EXT 0x35
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#define IDE_COMMAND_WRITE_QUEUE_EXT 0x36
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#define IDE_COMMAND_WRITE_EXT 0x34
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#define IDE_COMMAND_WRITE_MULTIPLE_EXT 0x39
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/*
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* IDE_COMMAND_SET_FEATURES
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*/
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#define FT_USE_ULTRA 0x40 /* Set feature for Ultra DMA */
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#define FT_USE_MWDMA 0x20 /* Set feature for MW DMA */
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#define FT_USE_SWDMA 0x10 /* Set feature for SW DMA */
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#define FT_USE_PIO 0x8 /* Set feature for PIO */
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#define FT_DISABLE_IORDY 0x10 /* Set feature for disabling IORDY */
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/*
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* S.M.A.R.T. commands
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*/
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#define IDE_COMMAND_SMART 0xB0
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#define SMART_READ_VALUES 0xd0
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#define SMART_READ_THRESHOLDS 0xd1
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#define SMART_AUTOSAVE 0xd2
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#define SMART_SAVE 0xd3
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#define SMART_IMMEDIATE_OFFLINE 0xd4
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#define SMART_READ_LOG_SECTOR 0xd5
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#define SMART_WRITE_LOG_SECTOR 0xd6
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#define SMART_ENABLE 0xd8
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#define SMART_DISABLE 0xd9
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#define SMART_STATUS 0xda
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#define SMART_AUTO_OFFLINE 0xdb
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/***************************************************************************
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* IDE Control Register File
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***************************************************************************/
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typedef struct _IDE_REGISTERS_2 {
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UCHAR AlternateStatus; /* RW: device control port */
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} IDE_REGISTERS_2, *PIDE_REGISTERS_2;
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/*
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* IDE drive control definitions
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*/
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#define IDE_DC_DISABLE_INTERRUPTS 0x02
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#define IDE_DC_RESET_CONTROLLER 0x04
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#define IDE_DC_REENABLE_CONTROLLER 0x00
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/***************************************************************************
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* MSNS: Removable device
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***************************************************************************/
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/*
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* Media syatus
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*/
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#define MSNS_NO_MEDIA 2
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#define MSNS_MEDIA_CHANGE_REQUEST 8
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#define MSNS_MIDIA_CHANGE 0x20
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#define MSNS_WRITE_PROTECT 0x40
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#define MSNS_READ_PROTECT 0x80
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/*
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* IDENTIFY data
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*/
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typedef struct _IDENTIFY_DATA {
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USHORT GeneralConfiguration; /* 00 00 */
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USHORT NumberOfCylinders; /* 02 1 */
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USHORT Reserved1; /* 04 2 */
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USHORT NumberOfHeads; /* 06 3 */
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USHORT UnformattedBytesPerTrack; /* 08 4 */
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USHORT UnformattedBytesPerSector; /* 0A 5 */
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USHORT SectorsPerTrack; /* 0C 6 */
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USHORT VendorUnique1[3]; /* 0E 7-9 */
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USHORT SerialNumber[10]; /* 14 10-19 */
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USHORT BufferType; /* 28 20 */
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USHORT BufferSectorSize; /* 2A 21 */
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USHORT NumberOfEccBytes; /* 2C 22 */
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USHORT FirmwareRevision[4]; /* 2E 23-26 */
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USHORT ModelNumber[20]; /* 36 27-46 */
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UCHAR MaximumBlockTransfer; /* 5E 47 */
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UCHAR VendorUnique2; /* 5F */
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USHORT DoubleWordIo; /* 60 48 */
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USHORT Capabilities; /* 62 49 */
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USHORT Reserved2; /* 64 50 */
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UCHAR VendorUnique3; /* 66 51 */
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UCHAR PioCycleTimingMode; /* 67 */
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UCHAR VendorUnique4; /* 68 52 */
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UCHAR DmaCycleTimingMode; /* 69 */
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USHORT TranslationFieldsValid; /* 6A 53 */
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USHORT NumberOfCurrentCylinders; /* 6C 54 */
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USHORT NumberOfCurrentHeads; /* 6E 55 */
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USHORT CurrentSectorsPerTrack; /* 70 56 */
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ULONG CurrentSectorCapacity; /* 72 57-58 */
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USHORT CurrentMultiSectorSetting; /* 76 59 */
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ULONG UserAddressableSectors; /* 78 60-61 */
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UCHAR SingleWordDMASupport; /* 7C 62 */
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UCHAR SingleWordDMAActive; /* 7D */
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UCHAR MultiWordDMASupport; /* 7E 63 */
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UCHAR MultiWordDMAActive; /* 7F */
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UCHAR AdvancedPIOModes; /* 80 64 */
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UCHAR Reserved4; /* 81 */
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USHORT MinimumMWXferCycleTime; /* 82 65 */
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USHORT RecommendedMWXferCycleTime; /* 84 66 */
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USHORT MinimumPIOCycleTime; /* 86 67 */
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USHORT MinimumPIOCycleTimeIORDY; /* 88 68 */
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USHORT Reserved5[2]; /* 8A 69-70 */
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USHORT ReleaseTimeOverlapped; /* 8E 71 */
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USHORT ReleaseTimeServiceCommand; /* 90 72 */
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USHORT MajorRevision; /* 92 73 */
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USHORT MinorRevision; /* 94 74 */
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USHORT MaxQueueDepth; /* 96 75 */
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USHORT SataCapability; /* 76 */
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USHORT Reserved6[9]; /* 98 77-85 */
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USHORT CommandSupport; /* 86 */
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USHORT CommandEnable; /* 87 */
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USHORT UtralDmaMode; /* 88 */
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USHORT Reserved7[11]; /* 89-99 */
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ULONG Lba48BitLow; /* 101-100 */
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ULONG Lba48BitHigh; /* 103-102 */
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USHORT Reserved8[23]; /* 104-126 */
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USHORT SpecialFunctionsEnabled; /* 127 */
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USHORT Reserved9[128]; /* 128-255 */
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} IDENTIFY_DATA, *PIDENTIFY_DATA;
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typedef struct _CONFIGURATION_IDENTIFY_DATA {
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USHORT Revision;
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USHORT MWDMAModeSupported;
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USHORT UDMAModeSupported;
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ULONG MaximumLbaLow;
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ULONG MaximumLbaHigh;
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USHORT CommandSupport;
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USHORT Reserved[247];
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UCHAR Signature; /* 0xA5 */
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UCHAR CheckSum;
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}
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CONFIGURATION_IDENTIFY_DATA, *PCONFIGURATION_IDENTIFY_DATA;
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/* */
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/* Identify data without the Reserved4. */
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/* */
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typedef struct _IDENTIFY_DATA2 {
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USHORT GeneralConfiguration; /* 00 00 */
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USHORT NumberOfCylinders; /* 02 1 */
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USHORT Reserved1; /* 04 2 */
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USHORT NumberOfHeads; /* 06 3 */
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USHORT UnformattedBytesPerTrack; /* 08 4 */
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USHORT UnformattedBytesPerSector; /* 0A 5 */
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USHORT SectorsPerTrack; /* 0C 6 */
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USHORT VendorUnique1[3]; /* 0E 7-9 */
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USHORT SerialNumber[10]; /* 14 10-19 */
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USHORT BufferType; /* 28 20 */
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USHORT BufferSectorSize; /* 2A 21 */
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USHORT NumberOfEccBytes; /* 2C 22 */
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USHORT FirmwareRevision[4]; /* 2E 23-26 */
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USHORT ModelNumber[20]; /* 36 27-46 */
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UCHAR MaximumBlockTransfer; /* 5E 47 */
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UCHAR VendorUnique2; /* 5F */
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USHORT DoubleWordIo; /* 60 48 */
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USHORT Capabilities; /* 62 49 */
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USHORT Reserved2; /* 64 50 */
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UCHAR VendorUnique3; /* 66 51 */
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UCHAR PioCycleTimingMode; /* 67 */
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UCHAR VendorUnique4; /* 68 52 */
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UCHAR DmaCycleTimingMode; /* 69 */
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USHORT TranslationFieldsValid; /* 6A 53 */
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USHORT NumberOfCurrentCylinders; /* 6C 54 */
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USHORT NumberOfCurrentHeads; /* 6E 55 */
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USHORT CurrentSectorsPerTrack; /* 70 56 */
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ULONG CurrentSectorCapacity; /* 72 57-58 */
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USHORT CurrentMultiSectorSetting; /* 59 */
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ULONG UserAddressableSectors; /* 60-61 */
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UCHAR SingleWordDMASupport; /* 62 */
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UCHAR SingleWordDMAActive;
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UCHAR MultiWordDMASupport; /* 63 */
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UCHAR MultiWordDMAActive;
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UCHAR AdvancedPIOModes; /* 64 */
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UCHAR Reserved4;
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USHORT MinimumMWXferCycleTime; /* 65 */
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USHORT RecommendedMWXferCycleTime; /* 66 */
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USHORT MinimumPIOCycleTime; /* 67 */
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USHORT MinimumPIOCycleTimeIORDY; /* 68 */
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USHORT Reserved5[2]; /* 69-70 */
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USHORT ReleaseTimeOverlapped; /* 71 */
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USHORT ReleaseTimeServiceCommand; /* 72 */
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USHORT MajorRevision; /* 73 */
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USHORT MinorRevision; /* 74 */
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/* USHORT Reserved6[14]; // 75-88 */
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} IDENTIFY_DATA2, *PIDENTIFY_DATA2;
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#define IDENTIFY_DATA_SIZE sizeof(IDENTIFY_DATA2)
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/* */
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/* IDENTIFY DMA timing cycle modes. */
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/* */
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#define IDENTIFY_DMA_CYCLES_MODE_0 0x00
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#define IDENTIFY_DMA_CYCLES_MODE_1 0x01
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#define IDENTIFY_DMA_CYCLES_MODE_2 0x02
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/*
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* Mode definitions
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*/
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typedef enum _DISK_MODE
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{
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IDE_PIO_0 = 0,
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IDE_PIO_1,
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IDE_PIO_2,
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IDE_PIO_3,
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IDE_PIO_4,
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IDE_MWDMA_0,
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IDE_MWDMA_1,
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IDE_MWDMA_2,
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IDE_UDMA_0,
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IDE_UDMA_1,
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IDE_UDMA_2,
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IDE_UDMA_3,
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IDE_UDMA_4,
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IDE_UDMA_5,
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IDE_UDMA_6,
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IDE_UDMA_7,
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} DISK_MODE;
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/***************************************************************************
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* IDE Macro
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***************************************************************************/
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#ifndef MAX_LBA_T
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#define MAX_LBA_T ((LBA_T)-1)
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#endif
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#define SECTOR_TO_BYTE_SHIFT 9
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#define SECTOR_TO_BYTE(x) ((ULONG)(x) << SECTOR_TO_BYTE_SHIFT)
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#define mGetStatus(IOPort2) (UCHAR)InPort(&IOPort2->AlternateStatus)
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#define mUnitControl(IOPort2, Value) OutPort(&IOPort2->AlternateStatus,(UCHAR)(Value))
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#define mGetErrorCode(IOPort) (UCHAR)InPort((PUCHAR)&IOPort->Data+1)
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#define mSetFeaturePort(IOPort,x) OutPort((PUCHAR)&IOPort->Data+1, x)
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#define mSetBlockCount(IOPort,x) OutPort(&IOPort->BlockCount, x)
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#define mGetBlockCount(IOPort) (UCHAR)InPort(&IOPort->BlockCount)
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#define mGetInterruptReason(IOPort) (UCHAR)InPort(&IOPort->BlockCount)
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#define mSetBlockNumber(IOPort,x) OutPort(&IOPort->BlockNumber, x)
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#define mGetBlockNumber(IOPort) (UCHAR)InPort((PUCHAR)&IOPort->BlockNumber)
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#define mGetByteLow(IOPort) (UCHAR)InPort(&IOPort->CylinderLow)
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#define mSetCylinderLow(IOPort,x) OutPort(&IOPort->CylinderLow, x)
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#define mGetByteHigh(IOPort) (UCHAR)InPort(&IOPort->CylinderHigh)
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#define mSetCylinderHigh(IOPort,x) OutPort(&IOPort->CylinderHigh, x)
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#define mGetBaseStatus(IOPort) (UCHAR)InPort(&IOPort->Command)
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#ifdef SUPPORT_HPT601
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#define mSelectUnit(IOPort,UnitId) do {\
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OutPort(&IOPort->DriveSelect, (UCHAR)(UnitId));\
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OutPort(&IOPort->DriveSelect, (UCHAR)(UnitId));\
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} while (0)
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#else
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#define mSelectUnit(IOPort,UnitId) OutPort(&IOPort->DriveSelect, (UCHAR)(UnitId))
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#endif
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#define mGetUnitNumber(IOPort) InPort(&IOPort->DriveSelect)
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#define mIssueCommand(IOPort,Cmd) OutPort(&IOPort->Command, (UCHAR)(Cmd))
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/*
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* WDC old disk, don't care right now
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*/
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#define WDC_MW1_FIX_FLAG_OFFSET 129
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#define WDC_MW1_FIX_FLAG_VALUE 0x00005555
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#pragma pack()
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#endif
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