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31a2c906d7
- Move DMA tag and map creature to at91_spi_activate() where the other
resource allocation also lives. [1]
- Flesh out at91_spi_deactivate(). [1]
- Work around the "Software Reset must be Written Twice" erratum.
- For now, run the bus at the slowest speed possible in order to work
around data corruption on transit even seen with 9 MHz on ETHERNUT5
(15 MHz maximum) and AT45DB321D (20 MHz maximum). This also serves as
a poor man's work-around for the "NPCSx rises if no data data is to be
transmitted" erratum of RM9200. Being able to use the appropriate bus
speed would require:
1) Adding a proper work-around for the RM9200 bug consisting of taking
the chip select control away from the SPI peripheral and managing it
directly as a GPIO line.
2) Taking the maximum frequencies supported by the actual board and the
slave devices into account and basing the whole thing on the master
clock instead of hardcoding a divisor as previously done.
3) Fixing the above mentioned data corruption.
- KASSERT that TX/RX command and data sizes match on transfers.
- Introduce a mutex ensuring that only one child device is running a SPI
transfer at a time. [1]
- Add preliminary, #ifdef'ed out support for setting the chip select. [1]
- Use the RX instead of the TX commando size when setting up the RX side
of a transfer.
- For controllers having SPI_SR_TXEMPTY, i.e. !RM9200, also wait for the
completion of the TX part of transfers before stopping the whole thing
again.
- Use DEVMETHOD_END. [1]
- Use NULL instead of 0 for pointers. [1, partially]
Additional testing by: Ian Lepore
Submitted by: Ian Lepore [1]
MFC after: 1 week
70 lines
2.8 KiB
C
70 lines
2.8 KiB
C
/*-
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* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef ARM_AT91_AT91_SPIREG_H
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#define ARM_AT91_AT91_SPIREG_H
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#define SPI_CR 0x00 /* CR: Control Register */
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#define SPI_CR_SPIEN 0x1
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#define SPI_CR_SPIDIS 0x2
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#define SPI_CR_SWRST 0x8
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#define SPI_MR 0x04 /* MR: Mode Register */
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#define SPI_MR_MSTR 0x01
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#define SPI_MR_PS 0x02
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#define SPI_MR_PCSDEC 0x04
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#define SPI_MR_DIV32 0x08
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#define SPI_MR_MODFDIS 0x10
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#define SPI_MR_LLB 0x80
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#define SPI_MR_PSC_CS0 0xe0000
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#define SPI_MR_PSC_CS1 0xd0000
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#define SPI_MR_PSC_CS2 0xb0000
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#define SPI_MR_PSC_CS3 0x70000
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#define SPI_RDR 0x08 /* RDR: Receive Data Register */
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#define SPI_TDR 0x0c /* TDR: Transmit Data Register */
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#define SPI_SR 0x10 /* SR: Status Register */
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#define SPI_SR_RDRF 0x00001
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#define SPI_SR_TDRE 0x00002
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#define SPI_SR_MODF 0x00004
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#define SPI_SR_OVRES 0x00008
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#define SPI_SR_ENDRX 0x00010
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#define SPI_SR_ENDTX 0x00020
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#define SPI_SR_RXBUFF 0x00040
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#define SPI_SR_TXBUFE 0x00080
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#define SPI_SR_NSSR 0x00100
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#define SPI_SR_TXEMPTY 0x00200
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#define SPI_SR_SPIENS 0x10000
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#define SPI_IER 0x14 /* IER: Interrupt Enable Regsiter */
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#define SPI_IDR 0x18 /* IDR: Interrupt Disable Regsiter */
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#define SPI_IMR 0x1c /* IMR: Interrupt Mask Regsiter */
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#define SPI_CSR0 0x30 /* CS0: Chip Select 0 */
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#define SPI_CSR_CPOL 0x01
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#define SPI_CSR1 0x34 /* CS1: Chip Select 1 */
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#define SPI_CSR2 0x38 /* CS2: Chip Select 2 */
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#define SPI_CSR3 0x3c /* CS3: Chip Select 3 */
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#endif /* ARM_AT91_AT91_SPIREG_H */
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