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134c58d3c0
the built-in 1000baseX interface in the Level 1 LXT1001 chip. The Level 1 PHY comes up with the isolate bit in the control register set by default, but it also has the autonegotiate bit set. When you tell the xmphy driver to select IFM_AUTO mode, it sees that the autoneg bit is already on, and thus doesn't bother updating the control register. However this means that the isolate bit is never turned off (unless you manually select 1000baseSX full or half duplex mode, which does result in the control register being modified and the ISO bit being turned off). This subtle and unusual behavioral difference stopped me from being able to receive packets on the SMC9462TX card for several days, since isolating the PHY disconnects it from the MAC's data interface. The fix is to omit the 'is the autoneg big set?' test, since it doesn't really provide much of an optimization anyway. This commit also updates the xmphy driver to support the Jato/Level 1 internal PHY. (I'm not sure how Jato Technologies is related to Level 1: all I know is the OUI from the PHY ID registers maps to Jato in the OUI database.) This will be used once I add the if_lge driver to support the LXT10010 chip.
118 lines
5.3 KiB
C
118 lines
5.3 KiB
C
/*
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* Copyright (c) 2000
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* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_MII_XMPHYREG_H_
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#define _DEV_MII_XMPHYREG_H_
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/*
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* XaQti XMAC II PHY registers
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*/
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#define XMPHY_MII_BMCR 0x00
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#define XMPHY_BMCR_RESET 0x8000
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#define XMPHY_BMCR_LOOP 0x4000
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#define XMPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
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#define XMPHY_BMCR_PDOWN 0x0800 /* Power down */
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#define XMPHY_BMCR_ISO 0x0400 /* Isolate */
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#define XMPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
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#define XMPHY_BMCR_FDX 0x0100 /* Duplex mode */
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#define XMPHY_MII_BMSR 0x01
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#define XMPHY_BMSR_EXTSTS 0x0100 /* Extended status present */
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#define XMPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */
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#define XMPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */
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#define XMPHY_BMSR_ANEG 0x0008 /* Autoneg capable */
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#define XMPHY_BMSR_LINK 0x0004 /* Link status */
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#define XMPHY_BMSR_EXT 0x0001 /* Extended capability */
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#define XMPHY_MII_ANAR 0x04
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#define XMPHY_ANAR_NP 0x8000 /* Next page */
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#define XMPHY_ANAR_ACK 0x4000 /* Next page or base received */
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#define XMPHY_ANAR_RFBITS 0x3000 /* Remote fault bits */
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#define XMPHY_ANAR_PAUSEBITS 0x0180 /* Pause bits */
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#define XMPHY_ANAR_FDX 0x0040 /* Select full duplex */
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#define XMPHY_ANAR_HDX 0x0020 /* Select half duplex */
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#define XMPHY_MII_ANLPAR 0x05
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#define XMPHY_ANLPAR_NP 0x8000 /* Next page */
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#define XMPHY_ANLPAR_ACK 0x4000 /* Next page or base received */
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#define XMPHY_ANLPAR_RFBITS 0x3000 /* Remote fault bits */
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#define XMPHY_ANLPAR_PAUSEBITS 0x0180 /* Pause bits */
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#define XMPHY_ANLPAR_FDX 0x0040 /* Select full duplex */
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#define XMPHY_ANLPAR_HDX 0x0020 /* Select half duplex */
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#define XMPHY_RF_OK 0x0000 /* No error -- link is good */
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#define XMPHY_RF_LINKFAIL 0x1000 /* Link failure */
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#define XMPHY_RF_OFFLINE 0x2000 /* Offline */
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#define XMPHY_RF_ANEGFAIL 0x3000 /* Autonegotiation error */
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#define XMPHY_PAUSE_NOPAUSE 0x0000 /* No pause possible */
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#define XMPHY_PAUSE_ASYMETRIC 0x0080 /* Asymetric pause toward LP */
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#define XMPHY_PAUSE_SYMETRIC 0x0100 /* Symetric pause */
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#define XMPHY_PAUSE_BOTH 0x0180 /* Both sym and asym pause */
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#define XMPHY_MII_ANER 0x06
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#define XMPHY_ANER_LPNP 0x0008 /* Link partner can next page */
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#define XMPHY_ANER_NP 0x0004 /* Local PHY can next page */
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#define XMPHY_ANER_RX 0x0002 /* Next page received */
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#define XMPHY_MII_NEXTP 0x07 /* Next page */
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#define XMPHY_NEXTP_MORE 0x8000 /* More next pages to follow */
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#define XMPHY_NEXTP_ACK1 0x4000 /* Ack bit received OK */
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#define XMPHY_NEXTP_MP 0x2000 /* Page is message page */
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#define XMPHY_NEXTP_ACK2 0x1000 /* can comply with message (r/o) */
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#define XMPHY_NEXTP_TOGGLE 0x0800 /* sync with LP */
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#define XMPHY_NEXTP_MESSAGE 0x07FF /* message */
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#define XMPHY_MII_NEXTPLP 0x08 /* Next page of link partner */
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#define XMPHY_NEXTPLP_MORE 0x8000 /* More next pages to follow */
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#define XMPHY_NEXTPLP_ACK1 0x4000 /* Ack bit received OK */
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#define XMPHY_NEXTPLP_MP 0x2000 /* Page is message page */
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#define XMPHY_NEXTPLP_ACK2 0x1000 /* can comply with message (r/o) */
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#define XMPHY_NEXTPLP_TOGGLE 0x0800 /* sync with LP */
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#define XMPHY_NEXTPLP_MESSAGE 0x07FF /* message */
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#define XMPHY_MII_EXTSTS 0x0F /* Extended status */
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#define XMPHY_EXTSTS_FDX 0x8000 /* 1000base-X FD capable */
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#define XMPHY_EXTSTS_HDX 0x4000 /* 1000base-X HD capable */
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#define XMPHY_MII_RESAB 0x10 /* Resolved ability */
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#define XMPHY_RESAB_PAUSEBITS 0x0180 /* Pause bits */
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#define XMPHY_RESAB_HDX 0x0040 /* Half duplex selected */
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#define XMPHY_RESAB_FDX 0x0020 /* Full duplex selected */
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#define XMPHY_RESAB_ABLMIS 0x0010 /* Ability mismatch */
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#define XMPHY_RESAB_PAUSEMIS 0x0008 /* Pause mismatch */
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#endif /* _DEV_MII_XMPHYREG_H_ */
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