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321 lines
12 KiB
C
321 lines
12 KiB
C
/*
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* All Rights Reserved, Copyright (C) Fujitsu Limited 1995
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*
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* This software may be used, modified, copied, distributed, and sold, in
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* both source and binary form provided that the above copyright, these
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* terms and the following disclaimer are retained. The name of the author
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* and/or the contributor may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND THE CONTRIBUTOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR THE CONTRIBUTOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#define FE_MB86960_H_VERSION "mb86960.h ver. 0.8"
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/*
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* Registers of Fujitsu MB86960A/MB86965A Ethernet controller.
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* Written and contributed by M.S. <seki@sysrap.cs.fujitsu.co.jp>
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*/
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/*
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* Notes on register naming:
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*
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* Fujitsu documents for MB86960A/MB86965A uses no mnemorable names
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* for their registers. They defined only three names for 32
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* registers and appended numbers to distinguish registers of
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* same name. Surprisingly, the numbers represent I/O address
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* offsets of the registers from the base addresses, and their
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* names correspond to the "bank" the registers are allocated.
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* All this means that, for example, to say "read DLCR8" has no more
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* than to say "read a register at offset 8 on bank DLCR."
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*
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* The following definitions may look silly, but that's what Fujitsu
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* did, and it is necessary to know these names to read Fujitsu
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* documents..
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*/
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/* Data Link Control Registrs, on invaliant port addresses. */
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#define FE_DLCR0 0
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#define FE_DLCR1 1
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#define FE_DLCR2 2
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#define FE_DLCR3 3
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#define FE_DLCR4 4
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#define FE_DLCR5 5
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#define FE_DLCR6 6
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#define FE_DLCR7 7
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/* More DLCRs, on register bank #0. */
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#define FE_DLCR8 8
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#define FE_DLCR9 9
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#define FE_DLCR10 10
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#define FE_DLCR11 11
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#define FE_DLCR12 12
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#define FE_DLCR13 13
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#define FE_DLCR14 14
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#define FE_DLCR15 15
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/* Malticast Address Registers. On register bank #1. */
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#define FE_MAR8 8
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#define FE_MAR9 9
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#define FE_MAR10 10
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#define FE_MAR11 11
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#define FE_MAR12 12
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#define FE_MAR13 13
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#define FE_MAR14 14
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#define FE_MAR15 15
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/* Buffer Memory Port Registers. On register back #2. */
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#define FE_BMPR8 8
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#define FE_BMPR9 9
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#define FE_BMPR10 10
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#define FE_BMPR11 11
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#define FE_BMPR12 12
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#define FE_BMPR13 13
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#define FE_BMPR14 14
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#define FE_BMPR15 15
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/* More BMPRs, only on MB86965A, accessible only when JLI mode. */
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#define FE_BMPR16 16
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#define FE_BMPR17 17
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#define FE_BMPR18 18
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#define FE_BMPR19 19
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/*
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* Definitions of registers.
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* I don't have Fujitsu documents of MB86960A/MB86965A, so I don't
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* know the official names for each flags and fields. The following
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* names are assigned by me (the author of this file,) since I cannot
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* mnemorize hexadecimal constants for all of these functions.
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* Comments? FIXME.
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*/
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/* DLCR0 -- transmitter status */
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#define FE_D0_BUSERR 0x01 /* Bus write error */
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#define FE_D0_COLL16 0x02 /* Collision limit (16) encountered */
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#define FE_D0_COLLID 0x04 /* Collision on last transmission */
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#define FE_D0_JABBER 0x08 /* Jabber */
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#define FE_D0_CRLOST 0x10 /* Carrier lost on last transmission */
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#define FE_D0_PKTRCD 0x20 /* No corrision on last transmission */
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#define FE_D0_NETBSY 0x40 /* Network Busy (Carrier Detected) */
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#define FE_D0_TXDONE 0x80 /* Transmission complete */
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/* DLCR1 -- receiver status */
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#define FE_D1_OVRFLO 0x01 /* Receiver buffer overflow */
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#define FE_D1_CRCERR 0x02 /* CRC error on last packet */
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#define FE_D1_ALGERR 0x04 /* Alignment error on last packet */
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#define FE_D1_SRTPKT 0x08 /* Short (RUNT) packet is received */
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#define FE_D1_RMTRST 0x10 /* Remote reset packet (type = 0x0900) */
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#define FE_D1_DMAEOP 0x20 /* Host asserted End of DMA OPeration */
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#define FE_D1_BUSERR 0x40 /* Bus read error */
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#define FE_D1_PKTRDY 0x80 /* Packet(s) ready on receive buffer */
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/* DLCR2 -- transmitter interrupt control; same layout as DLCR0 */
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#define FE_D2_BUSERR FE_D0_BUSERR
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#define FE_D2_COLL16 FE_D0_COLL16
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#define FE_D2_COLLID FE_D0_COLLID
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#define FE_D2_JABBER FE_D0_JABBER
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#define FE_D2_TXDONE FE_D0_TXDONE
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#define FE_D2_RESERVED 0x70
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/* DLCR3 -- receiver interrupt control; same layout as DLCR1 */
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#define FE_D3_OVRFLO FE_D1_OVRFLO
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#define FE_D3_CRCERR FE_D1_CRCERR
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#define FE_D3_ALGERR FE_D1_ALGERR
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#define FE_D3_SRTPKT FE_D1_SRTPKT
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#define FE_D3_RMTRST FE_D1_RMTRST
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#define FE_D3_DMAEOP FE_D1_DMAEOP
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#define FE_D3_BUSERR FE_D1_BUSERR
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#define FE_D3_PKTRDY FE_D1_PKTRDY
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/* DLCR4 -- transmitter operation mode */
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#define FE_D4_DSC 0x01 /* Disable carrier sense on trans. */
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#define FE_D4_LBC 0x02 /* Loop back test control */
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#define FE_D4_CNTRL 0x04 /* - ??? */
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#define FE_D4_TEST1 0x08 /* Test output #1 */
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#define FE_D4_COL 0xF0 /* Collision counter */
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#define FE_D4_LBC_ENABLE 0x00 /* Perform loop back test */
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#define FE_D4_LBC_DISABLE 0x02 /* Normal operation */
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#define FE_D4_COL_SHIFT 4
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/* DLCR5 -- receiver operation mode */
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#define FE_D5_AFM0 0x01 /* Receive packets for other stations */
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#define FE_D5_AFM1 0x02 /* Receive packets for this station */
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#define FE_D5_RMTRST 0x04 /* Enable remote reset operation */
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#define FE_D5_SRTPKT 0x08 /* Accept short (RUNT) packets */
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#define FE_D5_SRTADR 0x10 /* Short (16 bits?) MAC address */
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#define FE_D5_BADPKT 0x20 /* Accept packets with error */
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#define FE_D5_BUFEMP 0x40 /* Receive buffer is empty */
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#define FE_D5_TEST2 0x80 /* Test output #2 */
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/* DLCR6 -- hardware configuration #0 */
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#define FE_D6_BUFSIZ 0x03 /* Size of NIC buffer SRAM */
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#define FE_D6_TXBSIZ 0x0C /* Size (and config)of trans. buffer */
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#define FE_D6_BBW 0x10 /* Buffer SRAM bus width */
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#define FE_D6_SBW 0x20 /* System bus width */
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#define FE_D6_SRAM 0x40 /* Buffer SRAM access time */
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#define FE_D6_DLC 0x80 /* Disable DLC (recever/transmitter) */
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#define FE_D6_BUFSIZ_8KB 0x00 /* The board has 8KB SRAM */
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#define FE_D6_BUFSIZ_16KB 0x01 /* The board has 16KB SRAM */
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#define FE_D6_BUFSIZ_32KB 0x02 /* The board has 32KB SRAM */
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#define FE_D6_BUFSIZ_64KB 0x03 /* The board has 64KB SRAM */
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#define FE_D6_TXBSIZ_1x2KB 0x00 /* Single 2KB buffer for trans. */
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#define FE_D6_TXBSIZ_2x2KB 0x04 /* Double 2KB buffers */
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#define FE_D6_TXBSIZ_2x4KB 0x08 /* Double 4KB buffers */
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#define FE_D6_TXBSIZ_2x8KB 0x0C /* Double 8KB buffers */
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#define FE_D6_BBW_WORD 0x00 /* SRAM has 16 bit data line */
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#define FE_D6_BBW_BYTE 0x10 /* SRAM has 8 bit data line */
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#define FE_D6_SBW_WORD 0x00 /* Access with 16 bit (AT) bus */
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#define FE_D6_SBW_BYTE 0x20 /* Access with 8 bit (XT) bus */
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#define FE_D6_SRAM_150ns 0x00 /* The board has slow SRAM */
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#define FE_D6_SRAM_100ns 0x40 /* The board has fast SRAM */
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#define FE_D6_DLC_ENABLE 0x00 /* Normal operation */
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#define FE_D6_DLC_DISABLE 0x80 /* Stop sending/receiving */
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/* DLC7 -- hardware configuration #1 */
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#define FE_D7_BYTSWP 0x01 /* Host byte order control */
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#define FE_D7_EOPPOL 0x02 /* Polarity of DMA EOP signal */
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#define FE_D7_RBS 0x0C /* Register bank select */
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#define FE_D7_RDYPNS 0x10 /* Senses RDYPNSEL input signal */
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#define FE_D7_POWER 0x20 /* Stand-by (power down) mode control */
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#define FE_D7_IDENT 0xC0 /* Chip identification */
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#define FE_D7_BYTSWP_LH 0x00 /* DEC/Intel byte order */
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#define FE_D7_BYTSWP_HL 0x01 /* IBM/Motorolla byte order */
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#define FE_D7_RBS_DLCR 0x00 /* Select DLCR8-15 */
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#define FE_D7_RBS_MAR 0x04 /* Select MAR8-15 */
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#define FE_D7_RBS_BMPR 0x08 /* Select BMPR8-15 */
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#define FE_D7_POWER_DOWN 0x00 /* Power down (stand-by) mode */
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#define FE_D7_POWER_UP 0x20 /* Normal operation */
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#define FE_D7_IDENT_NICE 0x80
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#define FE_D7_IDENT_EC 0xC0
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/* DLCR8 thru DLCR13 are for Ethernet station address. */
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/* DLCR14 and DLCR15 are for TDR. (BTW, what is TDR? FIXME.) */
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/* MAR8 thru MAR15 are for Multicast address filter. */
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/* BMPR8 and BMPR9 are for packet data. */
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/* BMPR10 -- transmitter start trigger */
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#define FE_B10_START 0x80 /* Start transmitter */
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#define FE_B10_COUNT 0x7F /* Packet count */
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/* BMPR11 -- 16 collisions control */
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#define FE_B11_CTRL 0x01 /* Skip or resend errored packets */
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#define FE_B11_MODE1 0x02 /* Restart transmitter after COLL16 */
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#define FE_B11_MODE2 0x04 /* Automatic restart enable */
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#define FE_B11_CTRL_RESEND 0x00 /* Re-send the collided packet */
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#define FE_B11_CTRL_SKIP 0x01 /* Skip the collided packet */
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/* BMPR12 -- DMA enable */
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#define FE_B12_TXDMA 0x01 /* Enable transmitter DMA */
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#define FE_B12_RXDMA 0x02 /* Enable receiver DMA */
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/* BMPR13 -- DMA control */
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#define FE_B13_BSTCTL 0x03 /* DMA burst mode control */
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#define FE_B13_TPTYPE 0x04 /* Twisted pair cable impedance */
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#define FE_B13_PORT 0x18 /* Port (TP/AUI) selection */
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#define FE_B13_LNKTST 0x20 /* Link test enable */
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#define FE_B13_SQTHLD 0x40 /* Lower squelch threshold */
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#define FE_B13_IOUNLK 0x80 /* Change I/O base address */
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#define FE_B13_BSTCTL_1 0x00
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#define FE_B13_BSTCTL_4 0x01
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#define FE_B13_BSTCTL_8 0x02
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#define FE_B13_BSTCLT_12 0x03
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#define FE_B13_TPTYPE_UTP 0x00 /* Unshielded (standard) cable */
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#define FE_B13_TPTYPE_STP 0x04 /* Shielded (IBM) cable */
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#define FE_B13_PORT_AUTO 0x00 /* Auto detected */
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#define FE_B13_PORT_TP 0x08 /* Force TP */
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#define FE_B13_PORT_AUI 0x18 /* Force AUI */
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/* BMPR14 -- More receiver control and more transmission interrupts */
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#define FE_B14_FILTER 0x01 /* Filter out self-originated packets */
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#define FE_B14_SQE 0x02 /* SQE interrupt enable */
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#define FE_B14_SKIP 0x04 /* Skip a received packet */
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#define FE_B14_RJAB 0x20 /* RJAB interrupt enable */
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#define FE_B14_LLD 0x40 /* Local-link-down interrupt enable */
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#define FE_B14_RLD 0x80 /* Remote-link-down interrupt enable */
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/* BMPR15 -- More transmitter status; basically same layout as BMPR14 */
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#define FE_B15_SQE FE_B14_SQE
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#define FE_B15_RCVPOL 0x08 /* Reversed receive line polarity */
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#define FE_B15_RMTPRT 0x10 /* ??? */
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#define FE_B15_RAJB FE_B14_RJAB
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#define FE_B15_LLD FE_B14_LLD
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#define FE_B15_RLD FE_B14_RLD
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/* BMPR16 -- EEPROM control */
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#define FE_B16_DOUT 0x04 /* EEPROM Data in (CPU to EEPROM) */
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#define FE_B16_SELECT 0x20 /* EEPROM chip select */
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#define FE_B16_CLOCK 0x40 /* EEPROM shift clock */
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#define FE_B16_DIN 0x80 /* EEPROM data out (EEPROM to CPU) */
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/* BMPR17 -- EEPROM data */
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#define FE_B17_DATA 0x80 /* EEPROM data bit */
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/* BMPR18 ??? */
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/* BMPR19 -- ISA interface configuration */
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#define FE_B19_IRQ 0xC0
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#define FE_B19_IRQ_SHIFT 6
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#define FE_B19_ROM 0x38
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#define FE_B19_ROM_SHIFT 3
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#define FE_B19_ADDR 0x07
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#define FE_B19_ADDR_SHIFT 0
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/*
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* EEPROM specification (of JLI mode).
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*/
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/* Number of bytes in an EEPROM accessible through 86965. */
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#define FE_EEPROM_SIZE 32
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/* Offset for JLI config; automatically copied into BMPR19 at startup. */
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#define FE_EEPROM_CONF 0
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/*
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* Some 86960 specific constants.
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*/
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/* Length (in bytes) of a Multicast Address Filter. */
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#define FE_FILTER_LEN 8
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/* How many packets we can put in the transmission buffer on NIC memory. */
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#define FE_QUEUEING_MAX 127
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/* Length (in bytes) of a "packet length" word in transmission buffer. */
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#define FE_DATA_LEN_LEN 2
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/* Special Multicast Address Filter value. */
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#define FE_FILTER_NOTHING { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }
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#define FE_FILTER_ALL { 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF }
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