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179232d853
ePWM is controlled by sysctl nodes dev.am335x_pwm.N.period, dev.am335x_pwm.N.dutyA and dev.am335x_pwm.N.dutyB that controls PWM period and duty cycles for channels A and B respectively. Period and duty cycle are measured in clock ticks. Default clock frequency for AM335x PWM subsystem is 100MHz
427 lines
11 KiB
C
427 lines
11 KiB
C
/*-
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* Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/ti/ti_prcm.h>
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#include <arm/ti/ti_scm.h>
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#include "am335x_pwm.h"
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#include "am335x_scm.h"
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/* In ticks */
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#define DEFAULT_PWM_PERIOD 1000
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#define PWM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define PWM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define PWM_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \
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device_get_nameunit(_sc->sc_dev), "am335x_pwm softc", MTX_DEF)
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#define PWM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx);
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static struct resource_spec am335x_pwm_mem_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE }, /* PWMSS */
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{ SYS_RES_MEMORY, 1, RF_ACTIVE }, /* eCAP */
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{ SYS_RES_MEMORY, 2, RF_ACTIVE }, /* eQEP */
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{ SYS_RES_MEMORY, 3, RF_ACTIVE }, /*ePWM */
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{ -1, 0, 0 }
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};
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#define PWMSS_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res[0], reg);
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#define PWMSS_WRITE4(_sc, reg, value) \
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bus_write_4((_sc)->sc_mem_res[0], reg, value);
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#define ECAP_READ2(_sc, reg) bus_read_2((_sc)->sc_mem_res[1], reg);
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#define ECAP_WRITE2(_sc, reg, value) \
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bus_write_2((_sc)->sc_mem_res[1], reg, value);
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#define ECAP_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res[1], reg);
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#define ECAP_WRITE4(_sc, reg, value) \
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bus_write_4((_sc)->sc_mem_res[1], reg, value);
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#define EPWM_READ2(_sc, reg) bus_read_2((_sc)->sc_mem_res[3], reg);
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#define EPWM_WRITE2(_sc, reg, value) \
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bus_write_2((_sc)->sc_mem_res[3], reg, value);
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#define PWMSS_IDVER 0x00
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#define PWMSS_SYSCONFIG 0x04
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#define PWMSS_CLKCONFIG 0x08
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#define CLKCONFIG_EPWMCLK_EN (1 << 8)
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#define PWMSS_CLKSTATUS 0x0C
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#define ECAP_TSCTR 0x00
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#define ECAP_CAP1 0x08
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#define ECAP_CAP2 0x0C
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#define ECAP_CAP3 0x10
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#define ECAP_CAP4 0x14
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#define ECAP_ECCTL2 0x2A
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#define ECCTL2_MODE_APWM (1 << 9)
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#define ECCTL2_SYNCO_SEL (3 << 6)
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#define ECCTL2_TSCTRSTOP_FREERUN (1 << 4)
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#define EPWM_TBCTL 0x00
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#define TBCTL_FREERUN (2 << 14)
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#define TBCTL_PHDIR_UP (1 << 13)
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#define TBCTL_PHDIR_DOWN (0 << 13)
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#define TBCTL_CLKDIV(x) ((x) << 10)
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#define TBCTL_CLKDIV_MASK (3 << 10)
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#define TBCTL_HSPCLKDIV(x) ((x) << 7)
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#define TBCTL_HSPCLKDIV_MASK (3 << 7)
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#define TBCTL_SYNCOSEL_DISABLED (3 << 4)
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#define TBCTL_PRDLD_SHADOW (0 << 3)
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#define TBCTL_PRDLD_IMMEDIATE (0 << 3)
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#define TBCTL_PHSEN_ENABLED (1 << 2)
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#define TBCTL_PHSEN_DISABLED (0 << 2)
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#define TBCTL_CTRMODE_MASK (3)
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#define TBCTL_CTRMODE_UP (0 << 0)
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#define TBCTL_CTRMODE_DOWN (1 << 0)
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#define TBCTL_CTRMODE_UPDOWN (2 << 0)
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#define TBCTL_CTRMODE_FREEZE (3 << 0)
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#define EPWM_TBSTS 0x02
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#define EPWM_TBPHSHR 0x04
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#define EPWM_TBPHS 0x06
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#define EPWM_TBCNT 0x08
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#define EPWM_TBPRD 0x0a
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/* Counter-compare */
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#define EPWM_CMPCTL 0x0e
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#define CMPCTL_SHDWBMODE_SHADOW (1 << 6)
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#define CMPCTL_SHDWBMODE_IMMEDIATE (0 << 6)
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#define CMPCTL_SHDWAMODE_SHADOW (1 << 4)
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#define CMPCTL_SHDWAMODE_IMMEDIATE (0 << 4)
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#define CMPCTL_LOADBMODE_ZERO (0 << 2)
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#define CMPCTL_LOADBMODE_PRD (1 << 2)
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#define CMPCTL_LOADBMODE_EITHER (2 << 2)
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#define CMPCTL_LOADBMODE_FREEZE (3 << 2)
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#define CMPCTL_LOADAMODE_ZERO (0 << 0)
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#define CMPCTL_LOADAMODE_PRD (1 << 0)
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#define CMPCTL_LOADAMODE_EITHER (2 << 0)
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#define CMPCTL_LOADAMODE_FREEZE (3 << 0)
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#define EPWM_CMPAHR 0x10
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#define EPWM_CMPA 0x12
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#define EPWM_CMPB 0x14
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/* CMPCTL_LOADAMODE_ZERO */
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#define EPWM_AQCTLA 0x16
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#define EPWM_AQCTLB 0x18
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#define AQCTL_CBU_NONE (0 << 8)
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#define AQCTL_CBU_CLEAR (1 << 8)
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#define AQCTL_CBU_SET (2 << 8)
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#define AQCTL_CBU_TOGGLE (3 << 8)
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#define AQCTL_CAU_NONE (0 << 4)
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#define AQCTL_CAU_CLEAR (1 << 4)
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#define AQCTL_CAU_SET (2 << 4)
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#define AQCTL_CAU_TOGGLE (3 << 4)
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#define AQCTL_ZRO_NONE (0 << 0)
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#define AQCTL_ZRO_CLEAR (1 << 0)
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#define AQCTL_ZRO_SET (2 << 0)
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#define AQCTL_ZRO_TOGGLE (3 << 0)
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#define EPWM_AQSFRC 0x1a
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#define EPWM_AQCSFRC 0x1c
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/* Trip-Zone module */
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#define EPWM_TZCTL 0x28
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#define EPWM_TZFLG 0x2C
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/* High-Resolution PWM */
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#define EPWM_HRCTL 0x40
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#define HRCTL_DELMODE_BOTH 3
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#define HRCTL_DELMODE_FALL 2
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#define HRCTL_DELMODE_RISE 1
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static device_probe_t am335x_pwm_probe;
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static device_attach_t am335x_pwm_attach;
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static device_detach_t am335x_pwm_detach;
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struct am335x_pwm_softc {
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device_t sc_dev;
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struct mtx sc_mtx;
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struct resource *sc_mem_res[4];
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int sc_id;
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/* sysctl for configuration */
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struct sysctl_oid *sc_period_oid;
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struct sysctl_oid *sc_chanA_oid;
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struct sysctl_oid *sc_chanB_oid;
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uint32_t sc_pwm_period;
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uint32_t sc_pwm_dutyA;
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uint32_t sc_pwm_dutyB;
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};
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static device_method_t am335x_pwm_methods[] = {
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DEVMETHOD(device_probe, am335x_pwm_probe),
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DEVMETHOD(device_attach, am335x_pwm_attach),
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DEVMETHOD(device_detach, am335x_pwm_detach),
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DEVMETHOD_END
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};
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static driver_t am335x_pwm_driver = {
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"am335x_pwm",
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am335x_pwm_methods,
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sizeof(struct am335x_pwm_softc),
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};
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static devclass_t am335x_pwm_devclass;
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/*
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* API function to set period/duty cycles for ECASx
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*/
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int
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am335x_pwm_config_ecas(int unit, int period, int duty)
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{
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device_t dev;
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struct am335x_pwm_softc *sc;
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uint16_t reg;
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dev = devclass_get_device(am335x_pwm_devclass, unit);
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if (dev == NULL)
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return (ENXIO);
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if (duty > period)
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return (EINVAL);
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if (period == 0)
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return (EINVAL);
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sc = device_get_softc(dev);
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PWM_LOCK(sc);
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reg = ECAP_READ2(sc, ECAP_ECCTL2);
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reg |= ECCTL2_MODE_APWM | ECCTL2_TSCTRSTOP_FREERUN | ECCTL2_SYNCO_SEL;
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ECAP_WRITE2(sc, ECAP_ECCTL2, reg);
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/* CAP3 in APWM mode is APRD shadow register */
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ECAP_WRITE4(sc, ECAP_CAP3, period - 1);
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/* CAP4 in APWM mode is ACMP shadow register */
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ECAP_WRITE4(sc, ECAP_CAP4, duty);
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/* Restart counter */
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ECAP_WRITE4(sc, ECAP_TSCTR, 0);
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PWM_UNLOCK(sc);
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return (0);
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}
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static int
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am335x_pwm_sysctl_duty(SYSCTL_HANDLER_ARGS)
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{
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struct am335x_pwm_softc *sc = (struct am335x_pwm_softc*)arg1;
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int error;
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uint32_t duty;
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if (oidp == sc->sc_chanA_oid)
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duty = sc->sc_pwm_dutyA;
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else
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duty = sc->sc_pwm_dutyB;
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error = sysctl_handle_int(oidp, &duty, 0, req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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if (duty > sc->sc_pwm_period) {
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device_printf(sc->sc_dev, "Duty cycle can't be greater then period\n");
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return (EINVAL);
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}
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PWM_LOCK(sc);
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if (oidp == sc->sc_chanA_oid) {
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sc->sc_pwm_dutyA = duty;
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EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA);
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}
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else {
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sc->sc_pwm_dutyB = duty;
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EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB);
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}
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PWM_UNLOCK(sc);
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return (error);
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}
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static int
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am335x_pwm_sysctl_period(SYSCTL_HANDLER_ARGS)
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{
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struct am335x_pwm_softc *sc = (struct am335x_pwm_softc*)arg1;
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int error;
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uint32_t period;
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period = sc->sc_pwm_period;
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error = sysctl_handle_int(oidp, &period, 0, req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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if (period < 1)
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return (EINVAL);
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if ((period < sc->sc_pwm_dutyA) || (period < sc->sc_pwm_dutyB)) {
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device_printf(sc->sc_dev, "Period can't be less then duty cycle\n");
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return (EINVAL);
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}
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PWM_LOCK(sc);
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sc->sc_pwm_period = period;
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EPWM_WRITE2(sc, EPWM_TBPRD, period - 1);
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PWM_UNLOCK(sc);
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return (error);
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}
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static int
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am335x_pwm_probe(device_t dev)
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{
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if (!ofw_bus_is_compatible(dev, "ti,am335x-pwm"))
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return (ENXIO);
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device_set_desc(dev, "AM335x PWM");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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am335x_pwm_attach(device_t dev)
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{
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struct am335x_pwm_softc *sc;
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int err;
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uint32_t reg;
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phandle_t node;
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pcell_t did;
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struct sysctl_ctx_list *ctx;
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struct sysctl_oid *tree;
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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/* Get the PWM module id */
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node = ofw_bus_get_node(dev);
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if ((OF_getprop(node, "pwm-device-id", &did, sizeof(did))) <= 0) {
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device_printf(dev, "missing pwm-device-id attribute in FDT\n");
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return (ENXIO);
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}
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sc->sc_id = fdt32_to_cpu(did);
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PWM_LOCK_INIT(sc);
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err = bus_alloc_resources(dev, am335x_pwm_mem_spec,
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sc->sc_mem_res);
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if (err) {
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device_printf(dev, "cannot allocate memory resources\n");
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goto fail;
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}
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ti_prcm_clk_enable(PWMSS0_CLK + sc->sc_id);
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ti_scm_reg_read_4(SCM_PWMSS_CTRL, ®);
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reg |= (1 << sc->sc_id);
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ti_scm_reg_write_4(SCM_PWMSS_CTRL, reg);
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/* Init backlight interface */
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ctx = device_get_sysctl_ctx(sc->sc_dev);
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tree = device_get_sysctl_tree(sc->sc_dev);
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sc->sc_period_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
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"period", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
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am335x_pwm_sysctl_period, "I", "PWM period");
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sc->sc_chanA_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
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"dutyA", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
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am335x_pwm_sysctl_duty, "I", "Channel A duty cycles");
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sc->sc_chanB_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
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"dutyB", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
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am335x_pwm_sysctl_duty, "I", "Channel B duty cycles");
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/* CONFIGURE EPWM1 */
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reg = EPWM_READ2(sc, EPWM_TBCTL);
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reg &= ~(TBCTL_CLKDIV_MASK | TBCTL_HSPCLKDIV_MASK);
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EPWM_WRITE2(sc, EPWM_TBCTL, reg);
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sc->sc_pwm_period = DEFAULT_PWM_PERIOD;
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sc->sc_pwm_dutyA = 0;
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sc->sc_pwm_dutyB = 0;
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EPWM_WRITE2(sc, EPWM_TBPRD, sc->sc_pwm_period - 1);
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EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA);
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EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB);
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EPWM_WRITE2(sc, EPWM_AQCTLA, (AQCTL_ZRO_SET | AQCTL_CAU_CLEAR));
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EPWM_WRITE2(sc, EPWM_AQCTLB, (AQCTL_ZRO_SET | AQCTL_CBU_CLEAR));
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/* START EPWM */
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reg &= ~TBCTL_CTRMODE_MASK;
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reg |= TBCTL_CTRMODE_UP | TBCTL_FREERUN;
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EPWM_WRITE2(sc, EPWM_TBCTL, reg);
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EPWM_WRITE2(sc, EPWM_TZCTL, 0xf);
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reg = EPWM_READ2(sc, EPWM_TZFLG);
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return (0);
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fail:
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PWM_LOCK_DESTROY(sc);
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if (sc->sc_mem_res[0])
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bus_release_resources(dev, am335x_pwm_mem_spec,
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sc->sc_mem_res);
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return(ENXIO);
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}
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static int
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am335x_pwm_detach(device_t dev)
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{
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struct am335x_pwm_softc *sc;
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sc = device_get_softc(dev);
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PWM_LOCK(sc);
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if (sc->sc_mem_res[0])
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bus_release_resources(dev, am335x_pwm_mem_spec,
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sc->sc_mem_res);
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PWM_UNLOCK(sc);
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PWM_LOCK_DESTROY(sc);
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return (0);
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}
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DRIVER_MODULE(am335x_pwm, simplebus, am335x_pwm_driver, am335x_pwm_devclass, 0, 0);
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MODULE_VERSION(am335x_pwm, 1);
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MODULE_DEPEND(am335x_pwm, simplebus, 1, 1, 1);
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