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543 lines
12 KiB
C
543 lines
12 KiB
C
/**************************************************************************
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Copyright (c) 2009 Chelsio Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Neither the name of the Chelsio Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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***************************************************************************/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <cxgb_include.h>
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#undef msleep
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#define msleep t3_os_sleep
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enum {
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/* MDIO_DEV_PMA_PMD registers */
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AQ_LINK_STAT = 0xe800,
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/* MDIO_DEV_XGXS registers */
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AQ_XAUI_RX_CFG = 0xc400,
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AQ_XAUI_KX_CFG = 0xc440,
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AQ_XAUI_TX_CFG = 0xe400,
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/* MDIO_DEV_ANEG registers */
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AQ_100M_CTRL = 0x0010,
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AQ_10G_CTRL = 0x0020,
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AQ_1G_CTRL = 0xc400,
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AQ_ANEG_STAT = 0xc800,
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/* MDIO_DEV_VEND1 registers */
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AQ_FW_VERSION = 0x0020,
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AQ_THERMAL_THR = 0xc421,
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AQ_THERMAL1 = 0xc820,
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AQ_THERMAL2 = 0xc821,
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AQ_IFLAG_GLOBAL = 0xfc00,
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AQ_IMASK_GLOBAL = 0xff00,
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};
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#define AQBIT(x) (1 << (0x##x))
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#define ADV_1G_FULL AQBIT(f)
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#define ADV_1G_HALF AQBIT(e)
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#define ADV_10G_FULL AQBIT(c)
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#define AQ_WRITE_REGS(phy, regs) do { \
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int i; \
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for (i = 0; i < ARRAY_SIZE(regs); i++) { \
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(void) mdio_write(phy, regs[i].mmd, regs[i].reg, regs[i].val); \
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} \
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} while (0)
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#define AQ_READ_REGS(phy, regs) do { \
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unsigned i, v; \
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for (i = 0; i < ARRAY_SIZE(regs); i++) { \
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(void) mdio_read(phy, regs[i].mmd, regs[i].reg, &v); \
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} \
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} while (0)
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/*
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* Return value is temperature in celcius, 0xffff for error or don't know.
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*/
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static int
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aq100x_temperature(struct cphy *phy)
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{
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unsigned int v;
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if (mdio_read(phy, MDIO_DEV_VEND1, AQ_THERMAL2, &v) ||
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v == 0xffff || (v & 1) != 1)
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return (0xffff);
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if (mdio_read(phy, MDIO_DEV_VEND1, AQ_THERMAL1, &v))
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return (0xffff);
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return ((int)((signed char)(v >> 8)));
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}
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static int
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aq100x_set_defaults(struct cphy *phy)
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{
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return mdio_write(phy, MDIO_DEV_VEND1, AQ_THERMAL_THR, 0x6c00);
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}
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static int
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aq100x_reset(struct cphy *phy, int wait)
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{
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int err;
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err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait);
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if (!err)
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err = aq100x_set_defaults(phy);
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return (err);
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}
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static int
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aq100x_intr_enable(struct cphy *phy)
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{
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struct {
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int mmd;
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int reg;
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int val;
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} imasks[] = {
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{MDIO_DEV_VEND1, 0xd400, AQBIT(e)},
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{MDIO_DEV_VEND1, 0xff01, AQBIT(2)},
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{MDIO_DEV_VEND1, AQ_IMASK_GLOBAL, AQBIT(0)}
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};
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AQ_WRITE_REGS(phy, imasks);
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return (0);
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}
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static int
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aq100x_intr_disable(struct cphy *phy)
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{
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struct {
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int mmd;
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int reg;
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int val;
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} imasks[] = {
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{MDIO_DEV_VEND1, 0xd400, 0},
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{MDIO_DEV_VEND1, 0xff01, 0},
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{MDIO_DEV_VEND1, AQ_IMASK_GLOBAL, 0}
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};
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AQ_WRITE_REGS(phy, imasks);
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return (0);
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}
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static int
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aq100x_intr_clear(struct cphy *phy)
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{
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struct {
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int mmd;
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int reg;
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} iclr[] = {
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{MDIO_DEV_VEND1, 0xcc00},
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{MDIO_DEV_VEND1, AQ_IMASK_GLOBAL} /* needed? */
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};
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AQ_READ_REGS(phy, iclr);
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return (0);
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}
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static int
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aq100x_vendor_intr(struct cphy *phy, int *rc)
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{
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int err;
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unsigned int cause, v;
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err = mdio_read(phy, MDIO_DEV_VEND1, 0xfc01, &cause);
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if (err)
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return (err);
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if (cause & AQBIT(2)) {
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err = mdio_read(phy, MDIO_DEV_VEND1, 0xcc00, &v);
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if (err)
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return (err);
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if (v & AQBIT(e)) {
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CH_WARN(phy->adapter, "PHY%d: temperature is now %dC\n",
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phy->addr, aq100x_temperature(phy));
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t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN,
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phy->addr ? F_GPIO10_OUT_VAL : F_GPIO6_OUT_VAL, 0);
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*rc |= cphy_cause_alarm;
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}
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cause &= ~4;
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}
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if (cause)
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CH_WARN(phy->adapter, "PHY%d: unhandled vendor interrupt"
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" (0x%x)\n", phy->addr, cause);
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return (0);
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}
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static int
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aq100x_intr_handler(struct cphy *phy)
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{
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int err, rc = 0;
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unsigned int cause;
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err = mdio_read(phy, MDIO_DEV_VEND1, AQ_IFLAG_GLOBAL, &cause);
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if (err)
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return (err);
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if (cause & AQBIT(0)) {
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err = aq100x_vendor_intr(phy, &rc);
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if (err)
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return (err);
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cause &= ~AQBIT(0);
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}
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if (cause)
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CH_WARN(phy->adapter, "PHY%d: unhandled interrupt (0x%x)\n",
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phy->addr, cause);
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return (rc);
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}
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static int
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aq100x_power_down(struct cphy *phy, int off)
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{
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int err, wait = 500;
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unsigned int v;
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err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, BMCR_PDOWN,
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off ? BMCR_PDOWN : 0);
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if (err || off)
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return (err);
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msleep(300);
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do {
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err = mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMCR, &v);
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if (err)
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return (err);
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v &= BMCR_RESET;
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if (v)
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msleep(10);
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} while (v && --wait);
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if (v) {
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CH_WARN(phy->adapter, "PHY%d: power-up timed out (0x%x).\n",
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phy->addr, v);
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return (ETIMEDOUT);
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}
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return (0);
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}
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static int
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aq100x_autoneg_enable(struct cphy *phy)
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{
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int err;
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err = aq100x_power_down(phy, 0);
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if (!err)
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err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, MII_BMCR,
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BMCR_RESET, BMCR_ANENABLE | BMCR_ANRESTART);
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return (err);
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}
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static int
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aq100x_autoneg_restart(struct cphy *phy)
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{
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return aq100x_autoneg_enable(phy);
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}
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static int
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aq100x_advertise(struct cphy *phy, unsigned int advertise_map)
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{
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unsigned int adv;
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int err;
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/* 10G advertisement */
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adv = 0;
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if (advertise_map & ADVERTISED_10000baseT_Full)
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adv |= ADV_10G_FULL;
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err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, AQ_10G_CTRL,
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ADV_10G_FULL, adv);
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if (err)
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return (err);
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/* 1G advertisement */
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adv = 0;
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if (advertise_map & ADVERTISED_1000baseT_Full)
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adv |= ADV_1G_FULL;
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if (advertise_map & ADVERTISED_1000baseT_Half)
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adv |= ADV_1G_HALF;
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err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, AQ_1G_CTRL,
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ADV_1G_FULL | ADV_1G_HALF, adv);
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if (err)
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return (err);
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/* 100M, pause advertisement */
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adv = 0;
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if (advertise_map & ADVERTISED_100baseT_Half)
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adv |= ADVERTISE_100HALF;
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if (advertise_map & ADVERTISED_100baseT_Full)
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adv |= ADVERTISE_100FULL;
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if (advertise_map & ADVERTISED_Pause)
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adv |= ADVERTISE_PAUSE_CAP;
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if (advertise_map & ADVERTISED_Asym_Pause)
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adv |= ADVERTISE_PAUSE_ASYM;
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err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, AQ_100M_CTRL, 0xfe0, adv);
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return (err);
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}
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static int
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aq100x_set_loopback(struct cphy *phy, int mmd, int dir, int enable)
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{
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return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,
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BMCR_LOOPBACK, enable ? BMCR_LOOPBACK : 0);
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}
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static int
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aq100x_set_speed_duplex(struct cphy *phy, int speed, int duplex)
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{
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int err, set;
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if (speed == SPEED_100)
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set = BMCR_SPEED100;
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else if (speed == SPEED_1000)
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set = BMCR_SPEED1000;
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else if (speed == SPEED_10000)
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set = BMCR_SPEED1000 | BMCR_SPEED100;
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else
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return (EINVAL);
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if (duplex != DUPLEX_FULL)
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return (EINVAL);
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err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, MII_BMCR,
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BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART, 0);
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if (err)
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return (err);
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err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,
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BMCR_SPEED1000 | BMCR_SPEED100, set);
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if (err)
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return (err);
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return (0);
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}
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static int
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aq100x_get_link_status(struct cphy *phy, int *link_ok, int *speed, int *duplex,
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int *fc)
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{
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int err;
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unsigned int v, link = 0;
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err = mdio_read(phy, MDIO_DEV_PMA_PMD, AQ_LINK_STAT, &v);
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if (err)
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return (err);
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if (v == 0xffff || !(v & 1))
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goto done;
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err = mdio_read(phy, MDIO_DEV_ANEG, MII_BMCR, &v);
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if (err)
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return (err);
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if (v & 0x8000)
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goto done;
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if (v & BMCR_ANENABLE) {
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err = mdio_read(phy, MDIO_DEV_ANEG, 1, &v);
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if (err)
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return (err);
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if ((v & 0x20) == 0)
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goto done;
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err = mdio_read(phy, MDIO_DEV_ANEG, AQ_ANEG_STAT, &v);
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if (err)
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return (err);
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if (speed) {
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switch (v & 0x6) {
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case 0x6: *speed = SPEED_10000;
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break;
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case 0x4: *speed = SPEED_1000;
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break;
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case 0x2: *speed = SPEED_100;
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break;
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case 0x0: *speed = SPEED_10;
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break;
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}
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}
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if (duplex)
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*duplex = v & 1 ? DUPLEX_FULL : DUPLEX_HALF;
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if (fc) {
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unsigned int lpa, adv;
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err = mdio_read(phy, MDIO_DEV_ANEG, 0x13, &lpa);
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if (!err)
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err = mdio_read(phy, MDIO_DEV_ANEG,
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AQ_100M_CTRL, &adv);
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if (err)
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return err;
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if (lpa & adv & ADVERTISE_PAUSE_CAP)
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*fc = PAUSE_RX | PAUSE_TX;
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else if (lpa & ADVERTISE_PAUSE_CAP &&
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lpa & ADVERTISE_PAUSE_ASYM &&
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adv & ADVERTISE_PAUSE_ASYM)
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*fc = PAUSE_TX;
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else if (lpa & ADVERTISE_PAUSE_ASYM &&
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adv & ADVERTISE_PAUSE_CAP)
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*fc = PAUSE_RX;
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else
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*fc = 0;
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}
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} else {
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err = mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMCR, &v);
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if (err)
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return (err);
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v &= BMCR_SPEED1000 | BMCR_SPEED100;
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if (speed) {
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if (v == (BMCR_SPEED1000 | BMCR_SPEED100))
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*speed = SPEED_10000;
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else if (v == BMCR_SPEED1000)
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*speed = SPEED_1000;
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else if (v == BMCR_SPEED100)
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*speed = SPEED_100;
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else
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*speed = SPEED_10;
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}
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if (duplex)
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*duplex = DUPLEX_FULL;
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}
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link = 1;
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done:
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if (link_ok)
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*link_ok = link;
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return (0);
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}
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static struct cphy_ops aq100x_ops = {
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.reset = aq100x_reset,
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.intr_enable = aq100x_intr_enable,
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.intr_disable = aq100x_intr_disable,
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.intr_clear = aq100x_intr_clear,
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.intr_handler = aq100x_intr_handler,
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.autoneg_enable = aq100x_autoneg_enable,
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.autoneg_restart = aq100x_autoneg_restart,
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.advertise = aq100x_advertise,
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.set_loopback = aq100x_set_loopback,
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.set_speed_duplex = aq100x_set_speed_duplex,
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.get_link_status = aq100x_get_link_status,
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.power_down = aq100x_power_down,
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};
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int
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t3_aq100x_phy_prep(pinfo_t *pinfo, int phy_addr,
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const struct mdio_ops *mdio_ops)
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{
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struct cphy *phy = &pinfo->phy;
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unsigned int v, v2, gpio, wait;
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int err;
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adapter_t *adapter = pinfo->adapter;
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cphy_init(&pinfo->phy, adapter, pinfo, phy_addr, &aq100x_ops, mdio_ops,
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SUPPORTED_1000baseT_Full | SUPPORTED_10000baseT_Full |
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SUPPORTED_TP | SUPPORTED_Autoneg | SUPPORTED_AUI |
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SUPPORTED_MISC_IRQ, "1000/10GBASE-T");
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/*
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* Hard reset the PHY.
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*/
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gpio = phy_addr ? F_GPIO10_OUT_VAL : F_GPIO6_OUT_VAL;
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t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, gpio, 0);
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msleep(1);
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t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, gpio, gpio);
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/*
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* Give it enough time to load the firmware and get ready for mdio.
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*/
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msleep(1000);
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wait = 500; /* in 10ms increments */
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do {
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err = mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMCR, &v);
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if (err || v == 0xffff) {
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/* Allow prep_adapter to succeed when ffff is read */
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CH_WARN(adapter, "PHY%d: reset failed (0x%x, 0x%x).\n",
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phy_addr, err, v);
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goto done;
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}
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v &= BMCR_RESET;
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if (v)
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msleep(10);
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} while (v && --wait);
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if (v) {
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CH_WARN(adapter, "PHY%d: reset timed out (0x%x).\n",
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phy_addr, v);
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goto done; /* let prep_adapter succeed */
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}
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/* Firmware version check. */
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(void) mdio_read(phy, MDIO_DEV_VEND1, AQ_FW_VERSION, &v);
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if (v < 0x115)
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CH_WARN(adapter, "PHY%d: unknown firmware %d.%d\n", phy_addr,
|
|
v >> 8, v & 0xff);
|
|
|
|
/* The PHY should start in really-low-power mode. */
|
|
(void) mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMCR, &v);
|
|
if ((v & BMCR_PDOWN) == 0)
|
|
CH_WARN(adapter, "PHY%d does not start in low power mode.\n",
|
|
phy_addr);
|
|
|
|
/*
|
|
* Verify XAUI and 1000-X settings, but let prep succeed no matter what.
|
|
*/
|
|
v = v2 = 0;
|
|
(void) mdio_read(phy, MDIO_DEV_XGXS, AQ_XAUI_RX_CFG, &v);
|
|
(void) mdio_read(phy, MDIO_DEV_XGXS, AQ_XAUI_TX_CFG, &v2);
|
|
if (v != 0x1b || v2 != 0x1b)
|
|
CH_WARN(adapter, "PHY%d: incorrect XAUI settings "
|
|
"(0x%x, 0x%x).\n", phy_addr, v, v2);
|
|
v = 0;
|
|
(void) mdio_read(phy, MDIO_DEV_XGXS, AQ_XAUI_KX_CFG, &v);
|
|
if ((v & 0xf) != 0xf)
|
|
CH_WARN(adapter, "PHY%d: incorrect 1000-X settings "
|
|
"(0x%x).\n", phy_addr, v);
|
|
|
|
(void) aq100x_set_defaults(phy);
|
|
done:
|
|
return (err);
|
|
}
|