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d5a51e03e7
the AMI PCI controllers using the 8LD firmware interface (40LD firmware will be supported as soon as I have hardware to test with). These controllers are rebadged by Dell as the PERC, as well as by HP and possibly other vendors.
200 lines
6.0 KiB
C
200 lines
6.0 KiB
C
/*-
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* Copyright (c) 1999 Michael Smith
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Mailbox commands
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*/
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#define AMR_CMD_LREAD 0x01
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#define AMR_CMD_LWRITE 0x02
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#define AMR_CMD_ENQUIRY 0x05
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#define AMR_CMD_FLUSH 0x0a
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#define AMR_CMD_CONFIG 0xa1
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#define AMR_CONFIG_PRODINFO 0x0e
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#define AMR_CONFIG_ENQ3 0x0f
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#define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY 0x01
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#define AMR_CONFIG_ENQ3_SOLICITED_FULL 0x02
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#define AMR_CONFIG_ENQ3_UNSOLICITED 0x03
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/*
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* Command results
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*/
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#define AMR_STATUS_SUCCESS 0x00
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#define AMR_STATUS_ABORTED 0x02
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#define AMR_STATUS_FAILED 0x80
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/*
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* Quartz doorbell registers
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*/
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#define AMR_QIDB 0x20
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#define AMR_QODB 0x2c
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#define AMR_QIDB_SUBMIT 0x00000001 /* mailbox ready for work */
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#define AMR_QIDB_ACK 0x00000002 /* mailbox done */
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#define AMR_QODB_READY 0x10001234 /* work ready to be processed */
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/*
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* Standard I/O registers
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*/
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#define AMR_SCMD 0x10 /* command/ack register (write) */
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#define AMR_SMBOX_BUSY 0x10 /* mailbox status (read) */
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#define AMR_STOGGLE 0x11 /* interrupt enable bit here */
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#define AMR_SMBOX_0 0x14 /* mailbox physical address low byte */
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#define AMR_SMBOX_1 0x15
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#define AMR_SMBOX_2 0x16
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#define AMR_SMBOX_3 0x17 /* high byte */
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#define AMR_SMBOX_ENABLE 0x18 /* atomic mailbox address enable */
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#define AMR_SINTR 0x1a /* interrupt status */
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/*
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* Standard I/O magic numbers
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*/
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#define AMR_SCMD_POST 0x10 /* -> SCMD to initiate action on mailbox */
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#define AMR_SCMD_ACKINTR 0x08 /* -> SCMD to ack mailbox retrieved */
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#define AMR_STOGL_IENABLE 0xc0 /* in STOGGLE */
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#define AMR_SINTR_VALID 0x40 /* in SINTR */
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#define AMR_SMBOX_BUSYFLAG 0x10 /* in SMBOX_BUSY */
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#define AMR_SMBOX_ADDR 0x00 /* -> SMBOX_ENABLE */
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/*
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* Old Enquiry results
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*/
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#define AMR_8LD_MAXDRIVES 8
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#define AMR_8LD_MAXCHAN 5
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#define AMR_8LD_MAXTARG 15
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#define AMR_8LD_MAXPHYSDRIVES (AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG)
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struct amr_adapter_info
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{
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u_int8_t aa_maxio;
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u_int8_t aa_rebuild_rate;
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u_int8_t aa_maxtargchan;
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u_int8_t aa_channels;
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u_int8_t aa_firmware[4];
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u_int16_t aa_flashage;
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u_int8_t aa_chipsetvalue;
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u_int8_t aa_memorysize;
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u_int8_t aa_cacheflush;
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u_int8_t aa_bios[4];
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u_int8_t res1[7];
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} __attribute__ ((packed));
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struct amr_logdrive_info
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{
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u_int8_t al_numdrives;
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u_int8_t res1[3];
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u_int32_t al_size[AMR_8LD_MAXDRIVES];
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u_int8_t al_properties[AMR_8LD_MAXDRIVES];
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u_int8_t al_state[AMR_8LD_MAXDRIVES];
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} __attribute__ ((packed));
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struct amr_physdrive_info
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{
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u_int8_t ap_state[AMR_8LD_MAXPHYSDRIVES];
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u_int8_t res1;
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} __attribute__ ((packed));
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struct amr_enquiry
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{
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struct amr_adapter_info ae_adapter;
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struct amr_logdrive_info ae_ldrv;
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struct amr_physdrive_info ae_pdrv;
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} __attribute__ ((packed));
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struct amr_prodinfo
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{
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u_int32_t ap_size; /* current size in bytes (not including resvd) */
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u_int32_t ap_configsig; /* default is 0x00282008, indicating 0x28 maximum
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* logical drives, 0x20 maximum stripes and 0x08
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* maximum spans */
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u_int8_t ap_firmware[16]; /* printable identifiers */
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u_int8_t ap_bios[16];
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u_int8_t ap_product[80];
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u_int8_t ap_maxio; /* maximum number of concurrent commands supported */
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u_int8_t ap_nschan; /* number of SCSI channels present */
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u_int8_t ap_fcloops; /* number of fibre loops present */
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u_int8_t ap_memtype; /* memory type */
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u_int32_t ap_signature;
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u_int16_t ap_memsize; /* onboard memory in MB */
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u_int16_t ap_subsystem; /* subsystem identifier */
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u_int16_t ap_subvendor; /* subsystem vendor ID */
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u_int8_t ap_numnotifyctr; /* number of notify counters */
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} __attribute__((packed));
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#define AMR_MBOX_CMDSIZE 0x10 /* portion worth copying for controller */
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struct amr_mailbox
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{
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u_int8_t mb_command;
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u_int8_t mb_ident;
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u_int16_t mb_blkcount;
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u_int32_t mb_lba;
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u_int32_t mb_physaddr;
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u_int8_t mb_drive;
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u_int8_t mb_nsgelem;
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u_int8_t res1;
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u_int8_t mb_busy;
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u_int8_t mb_nstatus;
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u_int8_t mb_status;
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u_int8_t mb_completed[46];
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u_int8_t mb_poll;
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u_int8_t mb_ack;
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u_int8_t res2[16];
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} __attribute__ ((packed));
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struct amr_mailbox64
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{
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u_int32_t mb64_segment; /* for 64-bit controllers */
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struct amr_mailbox mb;
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} __attribute__ ((packed));
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struct amr_mailbox_ioctl
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{
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u_int8_t mb_command;
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u_int8_t mb_ident;
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u_int8_t mb_channel;
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u_int8_t mb_param;
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u_int8_t res1[4];
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u_int32_t mb_physaddr;
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u_int8_t mb_drive;
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u_int8_t mb_nsgelem;
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u_int8_t res2;
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u_int8_t mb_busy;
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u_int8_t mb_nstatus;
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u_int8_t mb_completed[46];
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u_int8_t mb_poll;
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u_int8_t mb_ack;
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u_int8_t res3[16];
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} __attribute__ ((packed));
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struct amr_sgentry
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{
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u_int32_t sg_addr;
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u_int32_t sg_count;
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} __attribute__ ((packed));
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