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f448abcd92
Add a %b printf descriptor Change the START command to DOWNLOAD to avoid confusion with start as in transmitting a packet.
481 lines
14 KiB
C
481 lines
14 KiB
C
/*
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* Copyright (C) 2000
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* Dr. Duncan McLennan Barclay, dmlb@ragnet.demon.co.uk.
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY DUNCAN BARCLAY AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL DUNCAN BARCLAY OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_rayreg.h,v 1.7 2000/03/21 14:26:38 dmlb Exp $
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*
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*/
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/* $NetBSD: if_rayreg.h,v 1.1 2000/01/23 23:59:22 chopps Exp $ */
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/*
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* Copyright (c) 2000 Christian E. Hopps
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* CCR registers, appearing in the attribute memory space
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*/
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#define RAY_CCR 0xf00 /* CCR register offset */
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#define RAY_COR (RAY_CCR + 0x00) /* config option register */
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#define RAY_CCSR (RAY_CCR + 0x01) /* config/status register */
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#define RAY_PIN (RAY_CCR + 0x02) /* not used by hw */
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#define RAY_SOCKETCOPY (RAY_CCR + 0x03) /* not used by hw */
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#define RAY_HCSIR (RAY_CCR + 0x05) /* HCS intr register */
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#define RAY_ECFIR (RAY_CCR + 0x06) /* ECF intr register */
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/*
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* We don't seem to be able to access these in a simple manner
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*/
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#define RAY_AR0 (RAY_CCR + 0x08) /* authorization register 0 (unused) */
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#define RAY_AR1 (RAY_CCR + 0x09) /* authorization register 1 (unused) */
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#define RAY_PMR (RAY_CCR + 0x0a) /* program mode register (unused) */
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#define RAY_TMR (RAY_CCR + 0x0b) /* pc test mode register (unused) */
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#define RAY_FCWR (RAY_CCR + 0x10) /* frequency control word register */
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#define RAY_TMC1 (RAY_CCR + 0x14) /* test mode control 1 (unused) */
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#define RAY_TMC2 (RAY_CCR + 0x15) /* test mode control 1 (unused) */
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#define RAY_TMC3 (RAY_CCR + 0x16) /* test mode control 1 (unused) */
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#define RAY_TMC4 (RAY_CCR + 0x17) /* test mode control 1 (unused) */
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/*
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* COR register bits
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*/
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#define RAY_COR_CFG_NUM 0x01 /* currently ignored and set */
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#define RAY_COR_CFG_MASK 0x3f /* mask for function */
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#define RAY_COR_LEVEL_IRQ 0x40 /* currently ignored and set */
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#define RAY_COR_RESET 0x80 /* soft-reset the card */
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#define RAY_COR_DEFAULT (RAY_COR_CFG_NUM | RAY_COR_LEVEL_IRQ)
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/*
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* CCS register bits
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*/
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#define RAY_CCS_NORMAL 0x00 /* normal operation */
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#define RAY_CCS_IRQ 0x02 /* interrupt pending */
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#define RAY_CCS_POWER_DOWN 0x04 /* when written powers down card */
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/*
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* HCSIR bits
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*
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* the host can only clear this bit.
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*/
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#define RAY_HCSIR_IRQ 0x01 /* indicates an interrupt */
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/*
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* ECFIR values
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*/
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#define RAY_ECFIR_IRQ 0x01 /* interrupt the card */
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/*
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* AR0 values
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* used for testing/programming the card (unused)
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*/
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#define RAY_AR0_ON 0x57
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/*
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* AR1 values
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* used for testing/programming the card (unused)
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*/
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#define RAY_AR1_ON 0x82
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/*
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* PMR bits
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* these are used to program the card (unused)
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*/
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#define RAY_PMR_NORMAL 0x00 /* normal operation */
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#define RAY_PMR_PC2PM 0x02 /* grant access to firmware flash */
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#define RAY_PMR_PC2CAL 0x10 /* read access to the A/D modem inp */
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#define RAY_PMR_MLSE 0x20 /* read access to the MSLE prom */
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/*
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* TMR bits
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* get access to test modes (unused)
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*/
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#define RAY_TMR_NORMAL 0x00 /* normal operation */
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#define RAY_TMR_TEST 0x08 /* test mode */
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/*
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* FCWR -- frequency control word, values from [0x02,0xA6] map to
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* RF frequency values.
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*/
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/*
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* 48k of memory
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*/
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#define RAY_SRAM_MEM_BASE 0
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#define RAY_SRAM_MEM_SIZE 0xc000
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/*
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* offsets into shared ram
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*/
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#define RAY_SCB_BASE 0x0000 /* cfg/status/ctl area */
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#define RAY_STATUS_BASE 0x0100
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#define RAY_HOST_TO_ECF_BASE 0x0200
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#define RAY_ECF_TO_HOST_BASE 0x0300
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#define RAY_CCS_BASE 0x0400
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#define RAY_RCS_BASE 0x0800
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#define RAY_APOINT_TIM_BASE 0x0c00
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#define RAY_SSID_LIST_BASE 0x0d00
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#define RAY_TX_BASE 0x1000
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#define RAY_TX_SIZE 0x7000
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#define RAY_TX_END 0x8000
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#define RAY_RX_BASE 0x8000
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#define RAY_RX_END 0xc000
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#define RAY_RX_MASK 0x3fff
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/*
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* Startup reporting stucture
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*/
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struct ray_ecf_startup_v4 {
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u_int8_t e_status;
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u_int8_t e_station_addr[ETHER_ADDR_LEN];
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u_int8_t e_prg_cksum;
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u_int8_t e_cis_cksum;
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u_int8_t e_resv0[7];
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u_int8_t e_japan_callsign[12];
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};
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struct ray_ecf_startup_v5 {
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u_int8_t e_status;
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u_int8_t e_station_addr[ETHER_ADDR_LEN];
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u_int8_t e_resv0;
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u_int8_t e_rates[8];
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u_int8_t e_japan_callsign[12];
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u_int8_t e_prg_cksum;
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u_int8_t e_cis_cksum;
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u_int8_t e_fw_build_string;
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u_int8_t e_fw_build;
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u_int8_t e_fw_resv;
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u_int8_t e_asic_version;
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u_int8_t e_tibsize;
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u_int8_t e_resv1[29];
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};
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/*
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* Startup status word result codes
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*/
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#define RAY_ECFS_RESERVED0 0x01
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#define RAY_ECFS_PROC_SELF_TEST 0x02
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#define RAY_ECFS_PROG_MEM_CHECKSUM 0x04
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#define RAY_ECFS_DATA_MEM_TEST 0x08
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#define RAY_ECFS_RX_CALIBRATION 0x10
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#define RAY_ECFS_FW_VERSION_COMPAT 0x20
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#define RAY_ECFS_RERSERVED1 0x40
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#define RAY_ECFS_TEST_COMPLETE 0x80
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#define RAY_ECFS_CARD_OK RAY_ECFS_TEST_COMPLETE
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#define RAY_ECFS_PRINTFB \
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"\020" \
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"\001RESERVED0" \
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"\002PROC_SELF_TEST" \
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"\003PROG_MEM_CHECKSUM" \
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"\004DATA_MEM_TEST" \
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"\005RX_CALIBRATION" \
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"\006FW_VERSION_COMPAT" \
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"\007RERSERVED1" \
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"\010TEST_COMPLETE"
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/*
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* Firmware build codes
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*/
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#define RAY_ECFS_BUILD_4 0x55
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#define RAY_ECFS_BUILD_5 0x5
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/*
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* System Control Block
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*/
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#define RAY_SCB_CCSI 0x00 /* host CCS index */
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#define RAY_SCB_RCSI 0x01 /* ecf RCS index */
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/*
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* command control structures (for CCSR commands)
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*/
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/*
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* commands for CCSR
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*/
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#define RAY_CMD_DOWNLOAD_PARAMS 0x01 /* download start params */
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#define RAY_CMD_UPDATE_PARAMS 0x02 /* update params */
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#define RAY_CMD_REPORT_PARAMS 0x03 /* report params */
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#define RAY_CMD_UPDATE_MCAST 0x04 /* update mcast list */
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#define RAY_CMD_UPDATE_APM 0x05 /* update power saving mode */
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#define RAY_CMD_START_NET 0x06
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#define RAY_CMD_JOIN_NET 0x07
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#define RAY_CMD_START_ASSOC 0x08
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#define RAY_CMD_TX_REQ 0x09
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#define RAY_CMD_TEST_MEM 0x0a
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#define RAY_CMD_SHUTDOWN 0x0b
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#define RAY_CMD_DUMP_MEM 0x0c
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#define RAY_CMD_START_TIMER 0x0d
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#define RAY_CMD_MAX 0x0e
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/*
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* unsolicted commands from the ECF
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*/
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#define RAY_ECMD_RX_DONE 0x80 /* process rx packet */
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#define RAY_ECMD_REJOIN_DONE 0x81 /* rejoined the network */
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#define RAY_ECMD_ROAM_START 0x82 /* romaining started */
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#define RAY_ECMD_JAPAN_CALL_SIGNAL 0x83 /* japan test thing */
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/*
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* Configure/status/control memory
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*/
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struct ray_csc {
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u_int8_t csc_mrxo_own; /* 0 ECF writes, 1 host write */
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u_int8_t csc_mrxc_own; /* 0 ECF writes, 1 host write */
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u_int8_t csc_rxhc_own; /* 0 ECF writes, 1 host write */
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u_int8_t csc_resv;
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u_int16_t csc_mrx_overflow; /* ECF incs on rx overflow */
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u_int16_t csc_mrx_cksum; /* ECF incs on cksum error */
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u_int16_t csc_rx_hcksum; /* ECF incs on header cksum error */
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u_int8_t csc_rx_noise; /* average RSL measuremant */
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};
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/*
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* CCS area
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*/
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#define RAY_CCS_LINK_NULL 0xff
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#define RAY_CCS_SIZE 16
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#define RAY_CCS_TX_FIRST 0
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#define RAY_CCS_TX_LAST 13
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#define RAY_CCS_NTX (RAY_CCS_TX_LAST - RAY_CCS_TX_FIRST + 1)
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#define RAY_TX_BUF_SIZE 2048
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#define RAY_CCS_CMD_FIRST 14
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#define RAY_CCS_CMD_LAST 63
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#define RAY_CCS_NCMD (RAY_CCS_CMD_LAST - RAY_CCS_CMD_FIRST + 1)
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#define RAY_CCS_LAST 63
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#define RAY_CCS_INDEX(ccs) (((ccs) - RAY_CCS_BASE) / RAY_CCS_SIZE)
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#define RAY_CCS_ADDRESS(i) (RAY_CCS_BASE + (i) * RAY_CCS_SIZE)
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/*
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* RCS area
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*/
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#define RAY_RCS_FIRST 64
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#define RAY_RCS_LAST 127
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/*
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* CCS commands
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*/
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struct ray_cmd {
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u_int8_t c_status; /* ccs generic header */
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u_int8_t c_cmd; /* " */
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u_int8_t c_link; /* " */
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};
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#define RAY_CCS_STATUS_FREE 0x0
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#define RAY_CCS_STATUS_BUSY 0x1
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#define RAY_CCS_STATUS_COMPLETE 0x2
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#define RAY_CCS_STATUS_FAIL 0x3
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#define RAY_CCS_STATUS_STRINGS { \
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"free", \
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"busy", \
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"complete", \
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"fail" \
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}
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/* RAY_CMD_UPDATE_PARAMS */
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struct ray_cmd_update {
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u_int8_t c_status; /* ccs generic header */
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u_int8_t c_cmd; /* " */
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u_int8_t c_link; /* " */
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u_int8_t c_paramid;
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u_int8_t c_nparam;
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u_int8_t c_failcause;
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};
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/* RAY_CMD_REPORT_PARAMS */
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struct ray_cmd_report {
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u_int8_t c_status; /* ccs generic header */
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u_int8_t c_cmd; /* " */
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u_int8_t c_link; /* " */
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u_int8_t c_paramid;
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u_int8_t c_nparam;
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u_int8_t c_failcause;
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u_int8_t c_len;
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};
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/* RAY_CMD_UPDATE_MCAST */
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struct ray_cmd_update_mcast {
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u_int8_t c_status; /* ccs generic header */
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u_int8_t c_cmd; /* " */
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u_int8_t c_link; /* " */
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u_int8_t c_nmcast;
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};
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/* RAY_CMD_UPDATE_APM */
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struct ray_cmd_udpate_apm {
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u_int8_t c_status; /* ccs generic header */
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u_int8_t c_cmd; /* " */
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u_int8_t c_link; /* " */
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u_int8_t c_mode;
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};
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/* RAY_CMD_START_NET and RAY_CMD_JOIN_NET */
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struct ray_cmd_net {
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u_int8_t c_status; /* ccs generic header */
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u_int8_t c_cmd; /* " */
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u_int8_t c_link; /* " */
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u_int8_t c_upd_param;
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u_int8_t c_bss_id[ETHER_ADDR_LEN];
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u_int8_t c_inited;
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u_int8_t c_def_txrate;
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u_int8_t c_encrypt;
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};
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/* Parameters passed in HOST_TO_ECF section when c_upd_param is set in
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* ray_cmd_net. */
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struct ray_net_params {
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u_int8_t p_net_type;
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u_int8_t p_ssid[32];
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u_int8_t p_privacy_must_start;
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u_int8_t p_privacy_can_join;
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};
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/* RAY_CMD_START_ASSOC */
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struct ray_cmd_update_assoc {
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u_int8_t c_status; /* ccs generic header */
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u_int8_t c_cmd; /* " */
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u_int8_t c_link; /* " */
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u_int8_t c_astatus;
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u_int8_t c_aid[2];
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};
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/* RAY_CMD_TX_REQ */
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struct ray_cmd_tx {
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u_int8_t c_status; /* ccs generic header */
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u_int8_t c_cmd; /* " */
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u_int8_t c_link; /* " */
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u_int8_t c_bufp[2];
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u_int8_t c_len[2];
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u_int8_t c_resv[5];
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u_int8_t c_tx_rate;
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u_int8_t c_apm_mode;
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u_int8_t c_nretry;
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u_int8_t c_antenna;
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};
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struct ray_cmd_tx_4 {
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u_int8_t c_status; /* ccs generic header */
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u_int8_t c_cmd; /* " */
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u_int8_t c_link; /* " */
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u_int8_t c_bufp[2];
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u_int8_t c_len[2];
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u_int8_t c_addr[ETHER_ADDR_LEN];
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u_int8_t c_apm_mode;
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u_int8_t c_nretry;
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u_int8_t c_antenna;
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};
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/* RAY_CMD_DUMP_MEM */
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struct ray_cmd_dump_mem {
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u_int8_t c_status; /* ccs generic header */
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u_int8_t c_cmd; /* " */
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u_int8_t c_link; /* " */
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u_int8_t c_memtype;
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u_int8_t c_memp[2];
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u_int8_t c_len;
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};
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/* RAY_CMD_START_TIMER */
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struct ray_cmd_start_timer {
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u_int8_t c_status; /* ccs generic header */
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u_int8_t c_cmd; /* " */
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u_int8_t c_link; /* " */
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u_int8_t c_duration[2];
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};
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/* RAY_ECMD_RX_DONE */
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struct ray_cmd_rx {
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u_int8_t c_status; /* ccs generic header */
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u_int8_t c_cmd; /* " */
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u_int8_t c_link; /* " */
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u_int8_t c_bufp[2]; /* buffer pointer */
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u_int8_t c_len[2]; /* length */
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u_int8_t c_siglev; /* signal level */
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u_int8_t c_nextfrag; /* next fragment in packet */
|
|
u_int8_t c_pktlen[2]; /* total packet length */
|
|
u_int8_t c_antenna; /* ant. with best reception */
|
|
u_int8_t c_updbss; /* only 1 for beacon messages */
|
|
};
|
|
|
|
/*
|
|
* Transmit scratch space and phy header structures
|
|
*/
|
|
struct ray_tx_tib {
|
|
u_int8_t t_ccs_index;
|
|
u_int8_t t_psm;
|
|
u_int8_t t_pass_fail;
|
|
u_int8_t t_retry_count;
|
|
u_int8_t t_max_retries;
|
|
u_int8_t t_frags_remaining;
|
|
u_int8_t t_no_rb;
|
|
u_int8_t t_rts_reqd;
|
|
u_int8_t t_csma_tx_cntrl_2;
|
|
u_int8_t t_sifs_tx_cntrl_2;
|
|
u_int8_t t_tx_dma_addr_1[2];
|
|
u_int8_t t_tx_dma_addr_2[2];
|
|
u_int8_t t_var_dur_2mhz[2];
|
|
u_int8_t t_var_dur_1mhz[2];
|
|
u_int8_t t_max_dur_2mhz[2];
|
|
u_int8_t t_max_dur_1mhz[2];
|
|
u_int8_t t_hdr_len;
|
|
u_int8_t t_max_frag_len[2];
|
|
u_int8_t t_var_len[2];
|
|
u_int8_t t_phy_hdr_4;
|
|
u_int8_t t_mac_hdr_1;
|
|
u_int8_t t_mac_hdr_2;
|
|
u_int8_t t_sid[2];
|
|
};
|
|
|
|
struct ray_tx_phy_header {
|
|
u_int8_t t_sfd[2];
|
|
u_int8_t t_hdr_3;
|
|
u_int8_t t_hdr_4;
|
|
};
|