Neel Natu 6be470c077 Add support for CPUs with cache coherent DMA. The two main changes are: ... - We don't need to fall back to uncacheable memory to satisfy BUS_DMA_COHERENT requests on these CPUs. - The bus_dmamap_sync() is a no-op for these CPUs. A side-effect of this change is rename DMAMAP_COHERENT flag to DMAMAP_UNCACHEABLE. This conveys the purpose of the flag more accurately. Reviewed by: gonzo, imp		2010-03-04 05:23:08 +00:00
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adm5120	- Call post-boot fixup function in order to get proper static	2010-01-25 00:44:05 +00:00
alchemy	Hack to make ALCHEMY compile again...	2010-02-18 19:41:38 +00:00
atheros	Define DMA_RX_STATUS_OVERFLOW with correct value.	2010-02-19 17:37:46 +00:00
cavium	Make printfs work for both OCTEON1 and OCTEON1-32	2010-02-18 19:27:00 +00:00
compile
conf	Get rid of unused options: KERNPHYSADDR, KERNVIRTADDR, PHYSADDR, PHYS_ADDR_64BIT	2010-02-20 06:39:14 +00:00
idt	- Call post-boot fixup function in order to get proper static	2010-01-25 00:44:05 +00:00
include	Add support for CPUs with cache coherent DMA. The two main changes are:	2010-03-04 05:23:08 +00:00
malta	The NetBSD Foundation has granted permission to remove clause 3 and 4 from	2010-03-03 17:55:51 +00:00
mips	Add support for CPUs with cache coherent DMA. The two main changes are:	2010-03-04 05:23:08 +00:00
rmi	The NetBSD Foundation has granted permission to remove clause 3 and 4 from	2010-03-03 17:55:51 +00:00
sentry5	- Call post-boot fixup function in order to get proper static	2010-01-25 00:44:05 +00:00
sibyte	Add support for CPUs with cache coherent DMA. The two main changes are:	2010-03-04 05:23:08 +00:00