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This is the final step required allowing to compile and to run RISC-V kernel and userland from HEAD. RISC-V is a completely open ISA that is freely available to academia and industry. Thanks to all the people involved! Special thanks to Andrew Turner, David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and Arun Thomas for their help. Thanks to Robert Watson for organizing this project. This project sponsored by UK Higher Education Innovation Fund (HEIF5) and DARPA CTSRD project at the University of Cambridge Computer Laboratory. FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv Reviewed by: andrew, emaste, kib Relnotes: Yes Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4982
14 lines
252 B
Plaintext
14 lines
252 B
Plaintext
#
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# DEFAULTS -- Default kernel configuration file for FreeBSD/RISC-V
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#
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# $FreeBSD$
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machine riscv riscv64
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# Pseudo devices.
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device mem # Memory and kernel memory devices
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# Default partitioning schemes
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options GEOM_PART_BSD
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options GEOM_PART_MBR
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