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81 lines
2.9 KiB
C
81 lines
2.9 KiB
C
/*
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* Copyright 1996 Massachusetts Institute of Technology
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*
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* Permission to use, copy, modify, and distribute this software and
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* its documentation for any purpose and without fee is hereby
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* granted, provided that both the above copyright notice and this
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* permission notice appear in all copies, that both the above
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* copyright notice and this permission notice appear in all
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* supporting documentation, and that the name of M.I.T. not be used
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* in advertising or publicity pertaining to distribution of the
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* software without specific, written prior permission. M.I.T. makes
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* no representations about the suitability of this software for any
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* purpose. It is provided "as is" without express or implied
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* warranty.
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*
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* THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
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* ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
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* SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id$
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*/
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#ifndef _PCI_WD82371REG_H_
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#define _PCI_WD82371REG_H_ 1
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/* Contents of IDETM register, as two 16-bit words (high ctlr 1, low ctlr 0) */
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#define IDETM_ENABLE 0x8000
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#define IDETM_IORDY_SAMP 0x3000 /* 00:5, 01:4, 10:3, 11:2 clocks */
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#define IDETM_RECOVERY_TIME 0x0300 /* 00:4, 01:3, 10:2, 11:1 clocks */
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#define IDETM_TIMING_ENB_1 0x0080
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#define IDETM_PREFETCH_POST_1 0x0040
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#define IDETM_ISP_ENB_1 0x0020 /* enabled IORDY sampling */
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#define IDETM_FAST_TIMING_1 0x0010
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#define IDETM_TIMING_ENB_0 0x0008
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#define IDETM_PREFETCH_POST_0 0x0004
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#define IDETM_ISP_ENB_0 0x0002
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#define IDETM_FAST_TIMING_0 0x0001
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#define IDETM_CTLR_0(x) (x)
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#define IDETM_CTLR_1(x) ((x) >> 16)
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/* Ports are for controller 0. Add PIIX_CTLR_1 for controller 1. */
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#define PIIX_CTLR_1 8
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/* Contents of BMICOM register */
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#define BMICOM_PORT 0
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#define BMICOM_READ_WRITE 0x0008 /* false = read, true = write */
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#define BMICOM_STOP_START 0x0001 /* false = stop, true = start */
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/* Contents of BMISTA register */
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#define BMISTA_PORT 2
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#define BMISTA_DMA1CAP 0x0040 /* true = drive 1 can DMA */
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#define BMISTA_DMA0CAP 0x0020 /* true = drive 0 can DMA */
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#define BMISTA_INTERRUPT 0x0004
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#define BMISTA_DMA_ERROR 0x0002
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#define BMISTA_DMA_ACTIVE 0x0001
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#define BMIDTP_PORT 4 /* use outl */
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struct piix_prd {
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u_int32_t prd_base;
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u_int16_t prd_eot;
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u_int16_t prd_count;
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};
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#define PRD_EOT_BIT 0x8000
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#define PRD_ALLOC_SIZE 4096
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#define PRD_MAX_SEGS (PRD_ALLOC_SIZE / 4)
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#endif /* _PCI_WD82371REG_H_ */
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