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7b7f33c4c3
chipsets. An example of this is the USB controller on these chipsets. With this, I can now use USB devices on the test Alpha I am borrowing at the moment. Reviewed by: dfr, obrien
446 lines
9.7 KiB
C
446 lines
9.7 KiB
C
/*
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/interrupt.h>
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#include <sys/sysctl.h>
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#include <sys/rman.h>
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#include <pci/pcivar.h>
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#include <machine/chipset.h>
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#include <machine/cpuconf.h>
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#include <machine/resource.h>
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#include <machine/md_var.h>
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#include <alpha/pci/pcibus.h>
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#include <alpha/isa/isavar.h>
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#include "isa.h"
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#define ISA_IRQ_OFFSET 0xe0
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#define ISA_IRQ_LEN 0x10
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char chipset_type[10];
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int chipset_bwx = 0;
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long chipset_ports = 0;
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long chipset_memory = 0;
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long chipset_dense = 0;
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long chipset_hae_mask = 0;
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SYSCTL_NODE(_hw, OID_AUTO, chipset, CTLFLAG_RW, 0, "PCI chipset information");
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SYSCTL_STRING(_hw_chipset, OID_AUTO, type, CTLFLAG_RD, chipset_type, 0,
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"PCI chipset type");
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SYSCTL_INT(_hw_chipset, OID_AUTO, bwx, CTLFLAG_RD, &chipset_bwx, 0,
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"PCI chipset supports BWX access");
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SYSCTL_LONG(_hw_chipset, OID_AUTO, ports, CTLFLAG_RD, &chipset_ports,
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"PCI chipset port address");
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SYSCTL_LONG(_hw_chipset, OID_AUTO, memory, CTLFLAG_RD, &chipset_memory,
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"PCI chipset memory address");
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SYSCTL_LONG(_hw_chipset, OID_AUTO, dense, CTLFLAG_RD, &chipset_dense,
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"PCI chipset dense memory address");
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SYSCTL_LONG(_hw_chipset, OID_AUTO, hae_mask, CTLFLAG_RD, &chipset_hae_mask,
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"PCI chipset mask for HAE register");
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#ifdef notyet
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/* return max number of devices on the bus */
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int
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pci_maxdevs(pcicfgregs *cfg)
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{
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return chipset.maxdevs(cfg->bus);
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}
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#endif
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/* read configuration space register */
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int
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pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
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{
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switch (bytes) {
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case 1:
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return chipset.cfgreadb(cfg->hose, cfg->bus,
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cfg->slot, cfg->func, reg);
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case 2:
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return chipset.cfgreadw(cfg->hose, cfg->bus,
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cfg->slot, cfg->func, reg);
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case 4:
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return chipset.cfgreadl(cfg->hose, cfg->bus,
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cfg->slot, cfg->func, reg);
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}
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return ~0;
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}
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/* write configuration space register */
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void
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pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
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{
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switch (bytes) {
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case 1:
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return chipset.cfgwriteb(cfg->hose, cfg->bus,
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cfg->slot, cfg->func, reg, data);
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case 2:
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return chipset.cfgwritew(cfg->hose, cfg->bus,
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cfg->slot, cfg->func, reg, data);
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case 4:
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return chipset.cfgwritel(cfg->hose, cfg->bus,
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cfg->slot, cfg->func, reg, data);
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}
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}
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vm_offset_t
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pci_cvt_to_dense(vm_offset_t sparse)
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{
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if(chipset.cvt_to_dense)
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return ALPHA_PHYS_TO_K0SEG(chipset.cvt_to_dense(sparse));
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else
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return NULL;
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}
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vm_offset_t
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pci_cvt_to_bwx(vm_offset_t sparse)
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{
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if(chipset.cvt_to_bwx)
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return ALPHA_PHYS_TO_K0SEG(chipset.cvt_to_bwx(sparse));
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else
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return NULL;
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}
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void
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alpha_platform_assign_pciintr(pcicfgregs *cfg)
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{
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if(platform.pci_intr_map)
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platform.pci_intr_map((void *)cfg);
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}
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#if NISA > 0
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struct resource *
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alpha_platform_alloc_ide_intr(int chan)
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{
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int irqs[2] = { 14, 15 };
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return isa_alloc_intr(0, 0, irqs[chan]);
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}
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int
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alpha_platform_release_ide_intr(int chan, struct resource *res)
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{
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return isa_release_intr(0, 0, res);
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}
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int
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alpha_platform_setup_ide_intr(struct resource *res,
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driver_intr_t *fn, void *arg,
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void **cookiep)
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{
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return isa_setup_intr(0, 0, res, INTR_TYPE_BIO, fn, arg, cookiep);
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}
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int
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alpha_platform_teardown_ide_intr(struct resource *res, void *cookie)
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{
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return isa_teardown_intr(0, 0, res, cookie);
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}
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#else
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struct resource *
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alpha_platform_alloc_ide_intr(int chan)
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{
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return (NULL);
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}
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int
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alpha_platform_release_ide_intr(int chan, struct resource *res)
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{
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return (ENXIO);
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}
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int
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alpha_platform_setup_ide_intr(struct resource *res,
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driver_intr_t *fn, void *arg, void **cookiep)
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{
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return (ENXIO);
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}
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int
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alpha_platform_teardown_ide_intr(struct resource *res, void *cookie)
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{
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return (ENXIO);
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}
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#endif
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static struct rman irq_rman, port_rman, mem_rman;
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int
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alpha_platform_pci_setup_intr(device_t dev, device_t child,
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struct resource *irq, int flags,
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driver_intr_t *intr, void *arg,
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void **cookiep)
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{
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/*
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* XXX - If we aren't the resource manager for this IRQ, assume that
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* it is actually handled by the ISA PIC.
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*/
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if(irq->r_rm != &irq_rman)
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return isa_setup_intr(dev, child, irq, flags, intr, arg,
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cookiep);
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else
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return bus_generic_setup_intr(dev, child, irq, flags, intr,
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arg, cookiep);
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}
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int
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alpha_platform_pci_teardown_intr(device_t dev, device_t child,
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struct resource *irq, void *cookie)
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{
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/*
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* XXX - If we aren't the resource manager for this IRQ, assume that
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* it is actually handled by the ISA PIC.
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*/
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if(irq->r_rm != &irq_rman)
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return isa_teardown_intr(dev, child, irq, cookie);
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else
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return bus_generic_teardown_intr(dev, child, irq, cookie);
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}
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void
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pci_init_resources(void)
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{
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irq_rman.rm_start = 0;
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irq_rman.rm_end = 65536;
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irq_rman.rm_type = RMAN_ARRAY;
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irq_rman.rm_descr = "PCI Mapped Interrupts";
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if (rman_init(&irq_rman)
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|| rman_manage_region(&irq_rman, 0, 65536))
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panic("pci_init_resources irq_rman");
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port_rman.rm_start = 0;
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port_rman.rm_end = ~0u;
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port_rman.rm_type = RMAN_ARRAY;
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port_rman.rm_descr = "I/O ports";
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if (rman_init(&port_rman)
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|| rman_manage_region(&port_rman, 0x0, (1L << 32)))
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panic("pci_init_resources port_rman");
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mem_rman.rm_start = 0;
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mem_rman.rm_end = ~0u;
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mem_rman.rm_type = RMAN_ARRAY;
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mem_rman.rm_descr = "I/O memory";
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if (rman_init(&mem_rman)
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|| rman_manage_region(&mem_rman, 0x0, (1L << 32)))
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panic("pci_init_resources mem_rman");
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}
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/*
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* Allocate a resource on behalf of child. NB: child is usually going to be a
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* child of one of our descendants, not a direct child of the pci chipset.
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*/
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struct resource *
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pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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struct rman *rm;
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struct resource *rv;
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switch (type) {
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case SYS_RES_IRQ:
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#if NISA > 0
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if((start >= ISA_IRQ_OFFSET) &&
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(end < ISA_IRQ_OFFSET + ISA_IRQ_LEN)) {
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return isa_alloc_intrs(bus, child,
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start - ISA_IRQ_OFFSET,
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end - ISA_IRQ_OFFSET);
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}
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else
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#endif
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rm = &irq_rman;
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break;
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case SYS_RES_IOPORT:
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rm = &port_rman;
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break;
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case SYS_RES_MEMORY:
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rm = &mem_rman;
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break;
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default:
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return 0;
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}
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rv = rman_reserve_resource(rm, start, end, count, flags, child);
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if (rv == 0)
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return 0;
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switch (type) {
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case SYS_RES_MEMORY:
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rman_set_bustag(rv, ALPHA_BUS_SPACE_MEM);
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rman_set_bushandle(rv, rv->r_start);
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if (flags & PCI_RF_DENSE)
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rman_set_virtual(rv, (void *) pci_cvt_to_dense(rv->r_start));
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else if (flags & PCI_RF_BWX)
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rman_set_virtual(rv, (void *) pci_cvt_to_bwx(rv->r_start));
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else
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rman_set_virtual(rv, (void *) rv->r_start); /* maybe NULL? */
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break;
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case SYS_RES_IOPORT:
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rman_set_bustag(rv, ALPHA_BUS_SPACE_IO);
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rman_set_bushandle(rv, rv->r_start);
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break;
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}
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return rv;
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}
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int
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pci_activate_resource(device_t bus, device_t child, int type, int rid,
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struct resource *r)
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{
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return (rman_activate_resource(r));
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}
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int
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pci_deactivate_resource(device_t bus, device_t child, int type, int rid,
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struct resource *r)
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{
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return (rman_deactivate_resource(r));
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}
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int
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pci_release_resource(device_t bus, device_t child, int type, int rid,
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struct resource *r)
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{
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return (rman_release_resource(r));
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}
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void
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memcpy_fromio(void *d, u_int32_t s, size_t size)
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{
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char *cp = d;
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while (size--)
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*cp++ = readb(s++);
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}
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void
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memcpy_toio(u_int32_t d, void *s, size_t size)
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{
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char *cp = s;
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while (size--)
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writeb(d++, *cp++);
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}
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void
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memcpy_io(u_int32_t d, u_int32_t s, size_t size)
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{
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while (size--)
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writeb(d++, readb(s++));
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}
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void
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memset_io(u_int32_t d, int val, size_t size)
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{
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while (size--)
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writeb(d++, val);
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}
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void
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memsetw(void *d, int val, size_t size)
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{
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u_int16_t *sp = d;
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while (size--)
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*sp++ = val;
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}
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void
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memsetw_io(u_int32_t d, int val, size_t size)
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{
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while (size--) {
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writew(d, val);
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d += sizeof(u_int16_t);
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}
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}
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#include "opt_ddb.h"
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#ifdef DDB
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#include <ddb/ddb.h>
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DB_COMMAND(in, db_in)
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{
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int c;
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int size;
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if (!have_addr)
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return;
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size = -1;
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while ((c = *modif++) != '\0') {
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switch (c) {
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case 'b':
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size = 1;
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break;
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case 'w':
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size = 2;
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break;
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case 'l':
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size = 4;
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break;
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}
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}
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if (size < 0) {
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db_printf("bad size\n");
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return;
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}
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if (count <= 0) count = 1;
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while (--count >= 0) {
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db_printf("%08lx:\t", addr);
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switch (size) {
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case 1:
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db_printf("%02x\n", inb(addr));
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break;
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case 2:
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db_printf("%04x\n", inw(addr));
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break;
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case 4:
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db_printf("%08x\n", inl(addr));
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break;
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}
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}
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}
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#endif
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