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756 lines
18 KiB
C
756 lines
18 KiB
C
/*-
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* Copyright 2007-2009 Solarflare Communications Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "efsys.h"
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#include "efx.h"
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#include "efx_types.h"
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#include "efx_regs.h"
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#include "efx_impl.h"
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#if EFSYS_OPT_FALCON
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#include "falcon_nvram.h"
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#endif
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#if EFSYS_OPT_MAC_FALCON_XMAC
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#include "falcon_xmac.h"
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#endif
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#if EFSYS_OPT_MAC_FALCON_GMAC
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#include "falcon_gmac.h"
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#endif
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#if EFSYS_OPT_PHY_NULL
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#include "nullphy.h"
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#endif
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#if EFSYS_OPT_PHY_QT2022C2
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#include "qt2022c2.h"
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#endif
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#if EFSYS_OPT_PHY_SFX7101
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#include "sfx7101.h"
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#endif
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#if EFSYS_OPT_PHY_TXC43128
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#include "txc43128.h"
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#endif
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#if EFSYS_OPT_PHY_SFT9001
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#include "sft9001.h"
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#endif
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#if EFSYS_OPT_PHY_QT2025C
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#include "qt2025c.h"
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#endif
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#if EFSYS_OPT_PHY_NULL
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static efx_phy_ops_t __cs __efx_phy_null_ops = {
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NULL, /* epo_power */
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nullphy_reset, /* epo_reset */
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nullphy_reconfigure, /* epo_reconfigure */
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nullphy_verify, /* epo_verify */
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NULL, /* epo_uplink_check */
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nullphy_downlink_check, /* epo_downlink_check */
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nullphy_oui_get, /* epo_oui_get */
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#if EFSYS_OPT_PHY_STATS
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nullphy_stats_update, /* epo_stats_update */
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#endif /* EFSYS_OPT_PHY_STATS */
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#if EFSYS_OPT_PHY_PROPS
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#if EFSYS_OPT_NAMES
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nullphy_prop_name, /* epo_prop_name */
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#endif
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nullphy_prop_get, /* epo_prop_get */
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nullphy_prop_set, /* epo_prop_set */
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#endif /* EFSYS_OPT_PHY_PROPS */
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#if EFSYS_OPT_PHY_BIST
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NULL, /* epo_bist_start */
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NULL, /* epo_bist_poll */
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NULL, /* epo_bist_stop */
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#endif /* EFSYS_OPT_PHY_BIST */
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};
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#endif /* EFSYS_OPT_PHY_NULL */
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#if EFSYS_OPT_PHY_QT2022C2
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static efx_phy_ops_t __cs __efx_phy_qt2022c2_ops = {
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NULL, /* epo_power */
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qt2022c2_reset, /* epo_reset */
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qt2022c2_reconfigure, /* epo_reconfigure */
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qt2022c2_verify, /* epo_verify */
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qt2022c2_uplink_check, /* epo_uplink_check */
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qt2022c2_downlink_check, /* epo_downlink_check */
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qt2022c2_oui_get, /* epo_oui_get */
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#if EFSYS_OPT_PHY_STATS
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qt2022c2_stats_update, /* epo_stats_update */
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#endif /* EFSYS_OPT_PHY_STATS */
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#if EFSYS_OPT_PHY_PROPS
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#if EFSYS_OPT_NAMES
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qt2022c2_prop_name, /* epo_prop_name */
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#endif
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qt2022c2_prop_get, /* epo_prop_get */
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qt2022c2_prop_set, /* epo_prop_set */
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#endif /* EFSYS_OPT_PHY_PROPS */
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#if EFSYS_OPT_PHY_BIST
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NULL, /* epo_bist_start */
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NULL, /* epo_bist_poll */
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NULL, /* epo_bist_stop */
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#endif /* EFSYS_OPT_PHY_BIST */
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};
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#endif /* EFSYS_OPT_PHY_QT2022C2 */
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#if EFSYS_OPT_PHY_SFX7101
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static efx_phy_ops_t __cs __efx_phy_sfx7101_ops = {
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sfx7101_power, /* epo_power */
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sfx7101_reset, /* epo_reset */
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sfx7101_reconfigure, /* epo_reconfigure */
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sfx7101_verify, /* epo_verify */
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sfx7101_uplink_check, /* epo_uplink_check */
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sfx7101_downlink_check, /* epo_downlink_check */
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sfx7101_oui_get, /* epo_oui_get */
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#if EFSYS_OPT_PHY_STATS
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sfx7101_stats_update, /* epo_stats_update */
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#endif /* EFSYS_OPT_PHY_STATS */
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#if EFSYS_OPT_PHY_PROPS
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#if EFSYS_OPT_NAMES
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sfx7101_prop_name, /* epo_prop_name */
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#endif
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sfx7101_prop_get, /* epo_prop_get */
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sfx7101_prop_set, /* epo_prop_set */
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#endif /* EFSYS_OPT_PHY_PROPS */
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#if EFSYS_OPT_PHY_BIST
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NULL, /* epo_bist_start */
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NULL, /* epo_bist_poll */
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NULL, /* epo_bist_stop */
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#endif /* EFSYS_OPT_PHY_BIST */
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};
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#endif /* EFSYS_OPT_PHY_SFX7101 */
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#if EFSYS_OPT_PHY_TXC43128
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static efx_phy_ops_t __cs __efx_phy_txc43128_ops = {
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NULL, /* epo_power */
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txc43128_reset, /* epo_reset */
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txc43128_reconfigure, /* epo_reconfigure */
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txc43128_verify, /* epo_verify */
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txc43128_uplink_check, /* epo_uplink_check */
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txc43128_downlink_check, /* epo_downlink_check */
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txc43128_oui_get, /* epo_oui_get */
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#if EFSYS_OPT_PHY_STATS
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txc43128_stats_update, /* epo_stats_update */
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#endif /* EFSYS_OPT_PHY_STATS */
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#if EFSYS_OPT_PHY_PROPS
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#if EFSYS_OPT_NAMES
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txc43128_prop_name, /* epo_prop_name */
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#endif
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txc43128_prop_get, /* epo_prop_get */
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txc43128_prop_set, /* epo_prop_set */
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#endif /* EFSYS_OPT_PHY_PROPS */
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#if EFSYS_OPT_PHY_BIST
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NULL, /* epo_bist_start */
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NULL, /* epo_bist_poll */
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NULL, /* epo_bist_stop */
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#endif /* EFSYS_OPT_PHY_BIST */
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};
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#endif /* EFSYS_OPT_PHY_TXC43128 */
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#if EFSYS_OPT_PHY_SFT9001
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static efx_phy_ops_t __cs __efx_phy_sft9001_ops = {
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NULL, /* epo_power */
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sft9001_reset, /* epo_reset */
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sft9001_reconfigure, /* epo_reconfigure */
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sft9001_verify, /* epo_verify */
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sft9001_uplink_check, /* epo_uplink_check */
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sft9001_downlink_check, /* epo_downlink_check */
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sft9001_oui_get, /* epo_oui_get */
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#if EFSYS_OPT_PHY_STATS
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sft9001_stats_update, /* epo_stats_update */
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#endif /* EFSYS_OPT_PHY_STATS */
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#if EFSYS_OPT_PHY_PROPS
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#if EFSYS_OPT_NAMES
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sft9001_prop_name, /* epo_prop_name */
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#endif
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sft9001_prop_get, /* epo_prop_get */
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sft9001_prop_set, /* epo_prop_set */
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#endif /* EFSYS_OPT_PHY_PROPS */
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#if EFSYS_OPT_PHY_BIST
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sft9001_bist_start, /* epo_bist_start */
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sft9001_bist_poll, /* epo_bist_poll */
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sft9001_bist_stop, /* epo_bist_stop */
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#endif /* EFSYS_OPT_PHY_BIST */
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};
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#endif /* EFSYS_OPT_PHY_SFT9001 */
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#if EFSYS_OPT_PHY_QT2025C
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static efx_phy_ops_t __cs __efx_phy_qt2025c_ops = {
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NULL, /* epo_power */
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qt2025c_reset, /* epo_reset */
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qt2025c_reconfigure, /* epo_reconfigure */
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qt2025c_verify, /* epo_verify */
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qt2025c_uplink_check, /* epo_uplink_check */
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qt2025c_downlink_check, /* epo_downlink_check */
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qt2025c_oui_get, /* epo_oui_get */
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#if EFSYS_OPT_PHY_STATS
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qt2025c_stats_update, /* epo_stats_update */
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#endif /* EFSYS_OPT_PHY_STATS */
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#if EFSYS_OPT_PHY_PROPS
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#if EFSYS_OPT_NAMES
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qt2025c_prop_name, /* epo_prop_name */
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#endif
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qt2025c_prop_get, /* epo_prop_get */
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qt2025c_prop_set, /* epo_prop_set */
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#endif /* EFSYS_OPT_PHY_PROPS */
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#if EFSYS_OPT_PHY_BIST
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NULL, /* epo_bist_start */
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NULL, /* epo_bist_poll */
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NULL, /* epo_bist_stop */
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#endif /* EFSYS_OPT_PHY_BIST */
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};
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#endif /* EFSYS_OPT_PHY_QT2025C */
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#if EFSYS_OPT_SIENA
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static efx_phy_ops_t __cs __efx_phy_siena_ops = {
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siena_phy_power, /* epo_power */
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NULL, /* epo_reset */
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siena_phy_reconfigure, /* epo_reconfigure */
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siena_phy_verify, /* epo_verify */
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NULL, /* epo_uplink_check */
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NULL, /* epo_downlink_check */
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siena_phy_oui_get, /* epo_oui_get */
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#if EFSYS_OPT_PHY_STATS
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siena_phy_stats_update, /* epo_stats_update */
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#endif /* EFSYS_OPT_PHY_STATS */
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#if EFSYS_OPT_PHY_PROPS
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#if EFSYS_OPT_NAMES
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siena_phy_prop_name, /* epo_prop_name */
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#endif
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siena_phy_prop_get, /* epo_prop_get */
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siena_phy_prop_set, /* epo_prop_set */
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#endif /* EFSYS_OPT_PHY_PROPS */
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#if EFSYS_OPT_PHY_BIST
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siena_phy_bist_start, /* epo_bist_start */
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siena_phy_bist_poll, /* epo_bist_poll */
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siena_phy_bist_stop, /* epo_bist_stop */
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#endif /* EFSYS_OPT_PHY_BIST */
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};
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#endif /* EFSYS_OPT_SIENA */
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__checkReturn int
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efx_phy_probe(
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__in efx_nic_t *enp)
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{
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efx_port_t *epp = &(enp->en_port);
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efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
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efx_phy_ops_t *epop;
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int rc;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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epp->ep_port = encp->enc_port;
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epp->ep_phy_type = encp->enc_phy_type;
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/* Hook in operations structure */
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switch (enp->en_family) {
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#if EFSYS_OPT_FALCON
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case EFX_FAMILY_FALCON:
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switch (epp->ep_phy_type) {
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#if EFSYS_OPT_PHY_NULL
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case PHY_TYPE_NONE_DECODE:
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epop = (efx_phy_ops_t *)&__efx_phy_null_ops;
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break;
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#endif
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#if EFSYS_OPT_PHY_QT2022C2
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case PHY_TYPE_QT2022C2_DECODE:
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epop = (efx_phy_ops_t *)&__efx_phy_qt2022c2_ops;
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break;
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#endif
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#if EFSYS_OPT_PHY_SFX7101
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case PHY_TYPE_SFX7101_DECODE:
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epop = (efx_phy_ops_t *)&__efx_phy_sfx7101_ops;
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break;
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#endif
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#if EFSYS_OPT_PHY_TXC43128
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case PHY_TYPE_TXC43128_DECODE:
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epop = (efx_phy_ops_t *)&__efx_phy_txc43128_ops;
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break;
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#endif
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#if EFSYS_OPT_PHY_SFT9001
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case PHY_TYPE_SFT9001A_DECODE:
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case PHY_TYPE_SFT9001B_DECODE:
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epop = (efx_phy_ops_t *)&__efx_phy_sft9001_ops;
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break;
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#endif
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#if EFSYS_OPT_PHY_QT2025C
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case EFX_PHY_QT2025C:
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epop = (efx_phy_ops_t *)&__efx_phy_qt2025c_ops;
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break;
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#endif
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default:
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rc = ENOTSUP;
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goto fail1;
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}
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break;
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#endif /* EFSYS_OPT_FALCON */
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#if EFSYS_OPT_SIENA
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case EFX_FAMILY_SIENA:
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epop = (efx_phy_ops_t *)&__efx_phy_siena_ops;
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break;
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#endif /* EFSYS_OPT_SIENA */
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default:
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rc = ENOTSUP;
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goto fail1;
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}
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epp->ep_epop = epop;
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return (0);
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fail1:
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EFSYS_PROBE1(fail1, int, rc);
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epp->ep_port = 0;
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epp->ep_phy_type = 0;
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return (rc);
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}
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__checkReturn int
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efx_phy_verify(
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__in efx_nic_t *enp)
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{
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efx_port_t *epp = &(enp->en_port);
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efx_phy_ops_t *epop = epp->ep_epop;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
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return (epop->epo_verify(enp));
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}
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#if EFSYS_OPT_PHY_LED_CONTROL
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__checkReturn int
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efx_phy_led_set(
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__in efx_nic_t *enp,
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__in efx_phy_led_mode_t mode)
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{
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efx_nic_cfg_t *encp = (&enp->en_nic_cfg);
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efx_port_t *epp = &(enp->en_port);
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efx_phy_ops_t *epop = epp->ep_epop;
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uint32_t mask;
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int rc;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
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if (epp->ep_phy_led_mode == mode)
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goto done;
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mask = (1 << EFX_PHY_LED_DEFAULT);
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mask |= encp->enc_led_mask;
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if (!((1 << mode) & mask)) {
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rc = ENOTSUP;
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goto fail1;
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}
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EFSYS_ASSERT3U(mode, <, EFX_PHY_LED_NMODES);
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epp->ep_phy_led_mode = mode;
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if ((rc = epop->epo_reconfigure(enp)) != 0)
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goto fail2;
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done:
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return (0);
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, int, rc);
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return (rc);
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}
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#endif /* EFSYS_OPT_PHY_LED_CONTROL */
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void
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efx_phy_adv_cap_get(
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__in efx_nic_t *enp,
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__in uint32_t flag,
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__out uint32_t *maskp)
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{
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efx_port_t *epp = &(enp->en_port);
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
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switch (flag) {
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case EFX_PHY_CAP_CURRENT:
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*maskp = epp->ep_adv_cap_mask;
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break;
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case EFX_PHY_CAP_DEFAULT:
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*maskp = epp->ep_default_adv_cap_mask;
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break;
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case EFX_PHY_CAP_PERM:
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*maskp = epp->ep_phy_cap_mask;
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break;
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default:
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EFSYS_ASSERT(B_FALSE);
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break;
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}
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}
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__checkReturn int
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efx_phy_adv_cap_set(
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__in efx_nic_t *enp,
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__in uint32_t mask)
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{
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efx_port_t *epp = &(enp->en_port);
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efx_phy_ops_t *epop = epp->ep_epop;
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int rc;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
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if ((mask & ~epp->ep_phy_cap_mask) != 0) {
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rc = ENOTSUP;
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goto fail1;
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}
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if (epp->ep_adv_cap_mask == mask)
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goto done;
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|
epp->ep_adv_cap_mask = mask;
|
|
|
|
if ((rc = epop->epo_reconfigure(enp)) != 0)
|
|
goto fail2;
|
|
|
|
done:
|
|
return (0);
|
|
|
|
fail2:
|
|
EFSYS_PROBE(fail2);
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, int, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
void
|
|
efx_phy_lp_cap_get(
|
|
__in efx_nic_t *enp,
|
|
__out uint32_t *maskp)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
|
|
|
|
*maskp = epp->ep_lp_cap_mask;
|
|
}
|
|
|
|
__checkReturn int
|
|
efx_phy_oui_get(
|
|
__in efx_nic_t *enp,
|
|
__out uint32_t *ouip)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
efx_phy_ops_t *epop = epp->ep_epop;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
|
|
|
|
return (epop->epo_oui_get(enp, ouip));
|
|
}
|
|
|
|
void
|
|
efx_phy_media_type_get(
|
|
__in efx_nic_t *enp,
|
|
__out efx_phy_media_type_t *typep)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
|
|
|
|
if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID)
|
|
*typep = epp->ep_module_type;
|
|
else
|
|
*typep = epp->ep_fixed_port_type;
|
|
}
|
|
|
|
#if EFSYS_OPT_PHY_STATS
|
|
|
|
#if EFSYS_OPT_NAMES
|
|
|
|
/* START MKCONFIG GENERATED PhyStatNamesBlock 271268f3da0e804f */
|
|
static const char __cs * __cs __efx_phy_stat_name[] = {
|
|
"oui",
|
|
"pma_pmd_link_up",
|
|
"pma_pmd_rx_fault",
|
|
"pma_pmd_tx_fault",
|
|
"pma_pmd_rev_a",
|
|
"pma_pmd_rev_b",
|
|
"pma_pmd_rev_c",
|
|
"pma_pmd_rev_d",
|
|
"pcs_link_up",
|
|
"pcs_rx_fault",
|
|
"pcs_tx_fault",
|
|
"pcs_ber",
|
|
"pcs_block_errors",
|
|
"phy_xs_link_up",
|
|
"phy_xs_rx_fault",
|
|
"phy_xs_tx_fault",
|
|
"phy_xs_align",
|
|
"phy_xs_sync_a",
|
|
"phy_xs_sync_b",
|
|
"phy_xs_sync_c",
|
|
"phy_xs_sync_d",
|
|
"an_link_up",
|
|
"an_master",
|
|
"an_local_rx_ok",
|
|
"an_remote_rx_ok",
|
|
"cl22ext_link_up",
|
|
"snr_a",
|
|
"snr_b",
|
|
"snr_c",
|
|
"snr_d",
|
|
"pma_pmd_signal_a",
|
|
"pma_pmd_signal_b",
|
|
"pma_pmd_signal_c",
|
|
"pma_pmd_signal_d",
|
|
"an_complete",
|
|
"pma_pmd_rev_major",
|
|
"pma_pmd_rev_minor",
|
|
"pma_pmd_rev_micro",
|
|
"pcs_fw_version_0",
|
|
"pcs_fw_version_1",
|
|
"pcs_fw_version_2",
|
|
"pcs_fw_version_3",
|
|
"pcs_fw_build_yy",
|
|
"pcs_fw_build_mm",
|
|
"pcs_fw_build_dd",
|
|
"pcs_op_mode",
|
|
};
|
|
|
|
/* END MKCONFIG GENERATED PhyStatNamesBlock */
|
|
|
|
const char __cs *
|
|
efx_phy_stat_name(
|
|
__in efx_nic_t *enp,
|
|
__in efx_phy_stat_t type)
|
|
{
|
|
_NOTE(ARGUNUSED(enp))
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(type, <, EFX_PHY_NSTATS);
|
|
|
|
return (__efx_phy_stat_name[type]);
|
|
}
|
|
|
|
#endif /* EFSYS_OPT_NAMES */
|
|
|
|
__checkReturn int
|
|
efx_phy_stats_update(
|
|
__in efx_nic_t *enp,
|
|
__in efsys_mem_t *esmp,
|
|
__out_ecount(EFX_PHY_NSTATS) uint32_t *stat)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
efx_phy_ops_t *epop = epp->ep_epop;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
|
|
|
|
return (epop->epo_stats_update(enp, esmp, stat));
|
|
}
|
|
|
|
#endif /* EFSYS_OPT_PHY_STATS */
|
|
|
|
#if EFSYS_OPT_PHY_PROPS
|
|
|
|
#if EFSYS_OPT_NAMES
|
|
const char __cs *
|
|
efx_phy_prop_name(
|
|
__in efx_nic_t *enp,
|
|
__in unsigned int id)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
efx_phy_ops_t *epop = epp->ep_epop;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
|
|
|
|
return (epop->epo_prop_name(enp, id));
|
|
}
|
|
#endif /* EFSYS_OPT_NAMES */
|
|
|
|
__checkReturn int
|
|
efx_phy_prop_get(
|
|
__in efx_nic_t *enp,
|
|
__in unsigned int id,
|
|
__in uint32_t flags,
|
|
__out uint32_t *valp)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
efx_phy_ops_t *epop = epp->ep_epop;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
|
|
|
|
return (epop->epo_prop_get(enp, id, flags, valp));
|
|
}
|
|
|
|
__checkReturn int
|
|
efx_phy_prop_set(
|
|
__in efx_nic_t *enp,
|
|
__in unsigned int id,
|
|
__in uint32_t val)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
efx_phy_ops_t *epop = epp->ep_epop;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
|
|
|
|
return (epop->epo_prop_set(enp, id, val));
|
|
}
|
|
#endif /* EFSYS_OPT_PHY_STATS */
|
|
|
|
#if EFSYS_OPT_PHY_BIST
|
|
|
|
__checkReturn int
|
|
efx_phy_bist_start(
|
|
__in efx_nic_t *enp,
|
|
__in efx_phy_bist_type_t type)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
efx_phy_ops_t *epop = epp->ep_epop;
|
|
int rc;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
|
|
|
|
EFSYS_ASSERT3U(type, !=, EFX_PHY_BIST_TYPE_UNKNOWN);
|
|
EFSYS_ASSERT3U(type, <, EFX_PHY_BIST_TYPE_NTYPES);
|
|
EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_PHY_BIST_TYPE_UNKNOWN);
|
|
|
|
if (epop->epo_bist_start == NULL) {
|
|
rc = ENOTSUP;
|
|
goto fail1;
|
|
}
|
|
|
|
if ((rc = epop->epo_bist_start(enp, type)) != 0)
|
|
goto fail2;
|
|
|
|
epp->ep_current_bist = type;
|
|
|
|
return (0);
|
|
|
|
fail2:
|
|
EFSYS_PROBE(fail2);
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, int, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
__checkReturn int
|
|
efx_phy_bist_poll(
|
|
__in efx_nic_t *enp,
|
|
__in efx_phy_bist_type_t type,
|
|
__out efx_phy_bist_result_t *resultp,
|
|
__out_opt uint32_t *value_maskp,
|
|
__out_ecount_opt(count) unsigned long *valuesp,
|
|
__in size_t count)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
efx_phy_ops_t *epop = epp->ep_epop;
|
|
int rc;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
|
|
|
|
EFSYS_ASSERT3U(type, !=, EFX_PHY_BIST_TYPE_UNKNOWN);
|
|
EFSYS_ASSERT3U(type, <, EFX_PHY_BIST_TYPE_NTYPES);
|
|
EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
|
|
|
|
EFSYS_ASSERT(epop->epo_bist_poll != NULL);
|
|
if (epop->epo_bist_poll == NULL) {
|
|
rc = ENOTSUP;
|
|
goto fail1;
|
|
}
|
|
|
|
if ((rc = epop->epo_bist_poll(enp, type, resultp, value_maskp,
|
|
valuesp, count)) != 0)
|
|
goto fail2;
|
|
|
|
return (0);
|
|
|
|
fail2:
|
|
EFSYS_PROBE(fail2);
|
|
fail1:
|
|
EFSYS_PROBE1(fail1, int, rc);
|
|
|
|
return (rc);
|
|
}
|
|
|
|
void
|
|
efx_phy_bist_stop(
|
|
__in efx_nic_t *enp,
|
|
__in efx_phy_bist_type_t type)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
efx_phy_ops_t *epop = epp->ep_epop;
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
|
|
|
|
EFSYS_ASSERT3U(type, !=, EFX_PHY_BIST_TYPE_UNKNOWN);
|
|
EFSYS_ASSERT3U(type, <, EFX_PHY_BIST_TYPE_NTYPES);
|
|
EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
|
|
|
|
EFSYS_ASSERT(epop->epo_bist_stop != NULL);
|
|
|
|
if (epop->epo_bist_stop != NULL)
|
|
epop->epo_bist_stop(enp, type);
|
|
|
|
epp->ep_current_bist = EFX_PHY_BIST_TYPE_UNKNOWN;
|
|
}
|
|
|
|
#endif /* EFSYS_OPT_PHY_BIST */
|
|
void
|
|
efx_phy_unprobe(
|
|
__in efx_nic_t *enp)
|
|
{
|
|
efx_port_t *epp = &(enp->en_port);
|
|
|
|
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
|
|
|
|
epp->ep_epop = NULL;
|
|
|
|
epp->ep_adv_cap_mask = 0;
|
|
|
|
epp->ep_port = 0;
|
|
epp->ep_phy_type = 0;
|
|
}
|