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581 lines
16 KiB
C
581 lines
16 KiB
C
/*
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*********************************************************************
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* FILE NAME : amd.h
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* BY : C.L. Huang (ching@tekram.com.tw)
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* Erich Chen (erich@tekram.com.tw)
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* Description: Device Driver for the amd53c974 PCI Bus Master
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* SCSI Host adapter found on cards such as
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* the Tekram DC-390(T).
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* (C)Copyright 1995-1999 Tekram Technology Co., Ltd.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*********************************************************************
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* $FreeBSD$
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*/
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#ifndef AMD_H
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#define AMD_H
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#define AMD_TRANS_CUR 0x01 /* Modify current neogtiation status */
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#define AMD_TRANS_ACTIVE 0x03 /* Assume this is the active target */
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#define AMD_TRANS_GOAL 0x04 /* Modify negotiation goal */
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#define AMD_TRANS_USER 0x08 /* Modify user negotiation settings */
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/*
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* Per target transfer parameters.
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*/
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struct amd_transinfo {
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u_int8_t period;
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u_int8_t offset;
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};
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struct amd_target_info {
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/*
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* Records the currently active and user/default settings for
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* tagged queueing and disconnection for each target.
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*/
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u_int8_t disc_tag;
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#define AMD_CUR_DISCENB 0x01
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#define AMD_CUR_TAGENB 0x02
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#define AMD_USR_DISCENB 0x04
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#define AMD_USR_TAGENB 0x08
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u_int8_t CtrlR1;
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u_int8_t CtrlR3;
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u_int8_t CtrlR4;
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u_int8_t sync_period_reg;
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u_int8_t sync_offset_reg;
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/*
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* Currently active transfer settings.
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*/
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struct amd_transinfo current;
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/*
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* Transfer settings we wish to achieve
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* through negotiation.
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*/
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struct amd_transinfo goal;
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/*
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* User defined or default transfer settings.
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*/
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struct amd_transinfo user;
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};
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/*
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* Scatter/Gather Segment entry.
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*/
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struct amd_sg {
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u_int32_t SGXLen;
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u_int32_t SGXPtr;
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};
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/*
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* Chipset feature limits
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*/
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#define MAX_SCSI_ID 8
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#define AMD_MAX_SYNC_OFFSET 15
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#define AMD_TARGET_MAX 7
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#define AMD_LUN_MAX 7
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#define AMD_NSEG (btoc(MAXPHYS) + 1)
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#define AMD_MAXTRANSFER_SIZE 0xFFFFFF /* restricted by 24 bit counter */
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#define MAX_DEVICES 10
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#define MAX_TAGS_CMD_QUEUE 256
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#define MAX_CMD_PER_LUN 6
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#define MAX_SRB_CNT 256
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#define MAX_START_JOB 256
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/*
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* BIT position to integer mapping.
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*/
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#define BIT(N) (0x01 << N)
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/*
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* EEPROM storage offsets and data structures.
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*/
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typedef struct _EEprom {
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u_int8_t EE_MODE1;
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u_int8_t EE_SPEED;
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u_int8_t xx1;
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u_int8_t xx2;
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} EEprom, *PEEprom;
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#define EE_ADAPT_SCSI_ID 64
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#define EE_MODE2 65
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#define EE_DELAY 66
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#define EE_TAG_CMD_NUM 67
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#define EE_DATA_SIZE 128
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#define EE_CHECKSUM 0x1234
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/*
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* EE_MODE1 bits definition
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*/
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#define PARITY_CHK BIT(0)
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#define SYNC_NEGO BIT(1)
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#define EN_DISCONNECT BIT(2)
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#define SEND_START BIT(3)
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#define TAG_QUEUING BIT(4)
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/*
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* EE_MODE2 bits definition
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*/
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#define MORE2_DRV BIT(0)
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#define GREATER_1G BIT(1)
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#define RST_SCSI_BUS BIT(2)
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#define ACTIVE_NEGATION BIT(3)
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#define NO_SEEK BIT(4)
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#define LUN_CHECK BIT(5)
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#define ENABLE_CE 1
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#define DISABLE_CE 0
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#define EEPROM_READ 0x80
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#define AMD_TAG_WILDCARD ((u_int)(~0))
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/*
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* SCSI Request Block
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*/
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struct amd_srb {
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TAILQ_ENTRY(amd_srb) links;
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u_int8_t CmdBlock[12];
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union ccb *pccb;
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bus_dmamap_t dmamap;
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struct amd_sg *pSGlist;
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u_int32_t TotalXferredLen;
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u_int32_t SGPhysAddr; /* a segment starting address */
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u_int32_t SGToBeXferLen; /* to be xfer length */
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u_int32_t Segment0[2];
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u_int32_t Segment1[2];
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struct amd_sg SGsegment[AMD_NSEG];
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struct amd_sg Segmentx;/* a one entry of S/G list table */
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u_int8_t *pMsgPtr;
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u_int16_t SRBState;
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u_int8_t AdaptStatus;
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u_int8_t TargetStatus;
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u_int8_t MsgCnt;
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u_int8_t EndMessage;
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u_int8_t TagNumber;
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u_int8_t SGcount;
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u_int8_t SGIndex;
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u_int8_t IORBFlag; /* ;81h-Reset, 2-retry */
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u_int8_t SRBStatus;
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u_int8_t SRBFlag;
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/* ; b0-AutoReqSense,b6-Read,b7-write */
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/* ; b4-settimeout,b5-Residual valid */
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u_int8_t ScsiCmdLen;
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};
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TAILQ_HEAD(srb_queue, amd_srb);
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/*
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* Per-adapter, software configuration.
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*/
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struct amd_softc {
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device_t dev;
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bus_space_tag_t tag;
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bus_space_handle_t bsh;
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bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
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int unit;
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int last_phase;
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int cur_target;
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int cur_lun;
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struct amd_srb *active_srb;
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struct amd_srb *untagged_srbs[AMD_TARGET_MAX+1][AMD_LUN_MAX+1];
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struct amd_target_info tinfo[AMD_TARGET_MAX+1];
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u_int16_t disc_count[AMD_TARGET_MAX+1][AMD_LUN_MAX+1];
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struct srb_queue free_srbs;
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struct srb_queue waiting_srbs;
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struct srb_queue running_srbs;
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struct amd_srb *pTmpSRB;
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u_int16_t SRBCount;
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u_int16_t max_id;
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u_int16_t max_lun;
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/* Hooks into the CAM XPT */
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struct cam_sim *psim;
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struct cam_path *ppath;
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u_int8_t msgin_buf[6];
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u_int8_t msgout_buf[6];
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u_int msgin_index;
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u_int msgout_index;
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u_int msgout_len;
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u_int8_t status;
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u_int8_t AdaptSCSIID; /* ; Adapter SCSI Target ID */
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u_int8_t AdaptSCSILUN; /* ; Adapter SCSI LUN */
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u_int8_t ACBFlag;
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u_int8_t Gmode2;
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u_int8_t HostID_Bit;
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u_int8_t InitDCB_flag[8][8]; /* flag of initDCB for device */
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struct amd_srb SRB_array[MAX_SRB_CNT]; /* +45Ch, Len= */
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struct amd_srb TmpSRB;
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/* Setup data stored in an 93c46 serial eeprom */
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u_int8_t eepromBuf[EE_DATA_SIZE];
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};
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/*
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* ----SRB State machine definition
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*/
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#define SRB_FREE 0
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#define SRB_READY BIT(1)
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#define SRB_MSGOUT BIT(2) /* ;arbitration+msg_out 1st byte */
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#define SRB_MSGIN BIT(3)
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#define SRB_MSGIN_MULTI BIT(4)
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#define SRB_COMMAND BIT(5)
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#define SRB_START BIT(6) /* ;arbitration+msg_out+command_out */
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#define SRB_DISCONNECT BIT(7)
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#define SRB_DATA_XFER BIT(8)
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#define SRB_XFERPAD BIT(9)
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#define SRB_STATUS BIT(10)
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#define SRB_COMPLETED BIT(11)
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#define SRB_ABORT_SENT BIT(12)
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#define DO_SYNC_NEGO BIT(13)
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#define SRB_UNEXPECT_RESEL BIT(14)
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/*
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* ---ACB Flag
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*/
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#define RESET_DEV BIT(0)
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#define RESET_DETECT BIT(1)
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#define RESET_DONE BIT(2)
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/*
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* ---DCB Flag
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*/
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#define ABORT_DEV_ BIT(0)
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/*
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* ---SRB status
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*/
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#define SRB_OK BIT(0)
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#define ABORTION BIT(1)
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#define OVER_RUN BIT(2)
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#define UNDER_RUN BIT(3)
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#define PARITY_ERROR BIT(4)
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#define SRB_ERROR BIT(5)
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/*
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* ---SRB Flags
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*/
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#define DATAOUT BIT(7)
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#define DATAIN BIT(6)
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#define RESIDUAL_VALID BIT(5)
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#define ENABLE_TIMER BIT(4)
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#define RESET_DEV0 BIT(2)
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#define ABORT_DEV BIT(1)
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#define AUTO_REQSENSE BIT(0)
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/*
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* ---Adapter status
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*/
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#define H_STATUS_GOOD 0
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#define H_SEL_TIMEOUT 0x11
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#define H_OVER_UNDER_RUN 0x12
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#define H_UNEXP_BUS_FREE 0x13
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#define H_TARGET_PHASE_F 0x14
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#define H_INVALID_CCB_OP 0x16
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#define H_LINK_CCB_BAD 0x17
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#define H_BAD_TARGET_DIR 0x18
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#define H_DUPLICATE_CCB 0x19
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#define H_BAD_CCB_OR_SG 0x1A
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#define H_ABORT 0x0FF
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/*
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* AMD specific "status" codes returned in the SCSI status byte.
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*/
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#define AMD_SCSI_STAT_UNEXP_BUS_F 0xFD /* ; Unexpect Bus Free */
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#define AMD_SCSI_STAT_BUS_RST_DETECT 0xFE /* ; Scsi Bus Reset detected */
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#define AMD_SCSI_STAT_SEL_TIMEOUT 0xFF /* ; Selection Time out */
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/*
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* ---Sync_Mode
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*/
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#define SYNC_DISABLE 0
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#define SYNC_ENABLE BIT(0)
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#define SYNC_NEGO_DONE BIT(1)
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#define WIDE_ENABLE BIT(2)
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#define WIDE_NEGO_DONE BIT(3)
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#define EN_TAG_QUEUING BIT(4)
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#define EN_ATN_STOP BIT(5)
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#define SYNC_NEGO_OFFSET 15
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/*
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* ---SCSI bus phase
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*/
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#define SCSI_DATA_OUT 0
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#define SCSI_DATA_IN 1
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#define SCSI_COMMAND 2
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#define SCSI_STATUS 3
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#define SCSI_NOP0 4
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#define SCSI_ARBITRATING 5
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#define SCSI_MSG_OUT 6
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#define SCSI_MSG_IN 7
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#define SCSI_BUS_FREE 8
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/*
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*==========================================================
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* AMD 53C974 Registers bit Definition
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*==========================================================
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*/
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/*
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* ------SCSI Register-------
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* Command Reg.(+0CH)
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*/
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#define DMA_COMMAND BIT(7)
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#define NOP_CMD 0
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#define CLEAR_FIFO_CMD 1
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#define RST_DEVICE_CMD 2
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#define RST_SCSI_BUS_CMD 3
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#define INFO_XFER_CMD 0x10
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#define INITIATOR_CMD_CMPLTE 0x11
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#define MSG_ACCEPTED_CMD 0x12
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#define XFER_PAD_BYTE 0x18
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#define SET_ATN_CMD 0x1A
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#define RESET_ATN_CMD 0x1B
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#define SEL_W_ATN 0x42
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#define SEL_W_ATN_STOP 0x43
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#define EN_SEL_RESEL 0x44
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#define SEL_W_ATN2 0x46
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#define DATA_XFER_CMD INFO_XFER_CMD
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/*
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* ------SCSI Register-------
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* SCSI Status Reg.(+10H)
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*/
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#define INTERRUPT BIT(7)
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#define ILLEGAL_OP_ERR BIT(6)
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#define PARITY_ERR BIT(5)
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#define COUNT_2_ZERO BIT(4)
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#define GROUP_CODE_VALID BIT(3)
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#define SCSI_PHASE_MASK (BIT(2)+BIT(1)+BIT(0))
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/*
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* ------SCSI Register-------
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* Interrupt Status Reg.(+14H)
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*/
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#define SCSI_RESET_ BIT(7)
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#define INVALID_CMD BIT(6)
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#define DISCONNECTED BIT(5)
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#define SERVICE_REQUEST BIT(4)
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#define SUCCESSFUL_OP BIT(3)
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#define RESELECTED BIT(2)
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#define SEL_ATTENTION BIT(1)
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#define SELECTED BIT(0)
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/*
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* ------SCSI Register-------
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* Internal State Reg.(+18H)
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*/
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#define SYNC_OFFSET_FLAG BIT(3)
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#define INTRN_STATE_MASK (BIT(2)+BIT(1)+BIT(0))
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/*
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* ------SCSI Register-------
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* Clock Factor Reg.(+24H)
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*/
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#define CLK_FREQ_40MHZ 0
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#define CLK_FREQ_35MHZ (BIT(2)+BIT(1)+BIT(0))
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#define CLK_FREQ_30MHZ (BIT(2)+BIT(1))
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#define CLK_FREQ_25MHZ (BIT(2)+BIT(0))
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#define CLK_FREQ_20MHZ BIT(2)
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#define CLK_FREQ_15MHZ (BIT(1)+BIT(0))
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#define CLK_FREQ_10MHZ BIT(1)
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/*
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* ------SCSI Register-------
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* Control Reg. 1(+20H)
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*/
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#define EXTENDED_TIMING BIT(7)
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#define DIS_INT_ON_SCSI_RST BIT(6)
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#define PARITY_ERR_REPO BIT(4)
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#define SCSI_ID_ON_BUS (BIT(2)+BIT(1)+BIT(0))
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/*
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* ------SCSI Register-------
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* Control Reg. 2(+2CH)
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*/
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#define EN_FEATURE BIT(6)
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#define EN_SCSI2_CMD BIT(3)
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/*
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* ------SCSI Register-------
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* Control Reg. 3(+30H)
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*/
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#define ID_MSG_CHECK BIT(7)
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#define EN_QTAG_MSG BIT(6)
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#define EN_GRP2_CMD BIT(5)
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#define FAST_SCSI BIT(4) /* ;10MB/SEC */
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#define FAST_CLK BIT(3) /* ;25 - 40 MHZ */
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/*
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* ------SCSI Register-------
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* Control Reg. 4(+34H)
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*/
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#define EATER_12NS 0
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#define EATER_25NS BIT(7)
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#define EATER_35NS BIT(6)
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#define EATER_0NS (BIT(7)+BIT(6))
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#define NEGATE_REQACKDATA BIT(2)
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#define NEGATE_REQACK BIT(3)
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/*
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*========================================
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* DMA Register
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*========================================
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*/
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/*
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* -------DMA Register--------
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* DMA Command Reg.(+40H)
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*/
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#define READ_DIRECTION BIT(7)
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#define WRITE_DIRECTION 0
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#define EN_DMA_INT BIT(6)
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#define MAP_TO_MDL BIT(5)
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#define DMA_DIAGNOSTIC BIT(4)
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#define DMA_IDLE_CMD 0
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#define DMA_BLAST_CMD BIT(0)
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#define DMA_ABORT_CMD BIT(1)
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#define DMA_START_CMD (BIT(1)|BIT(0))
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/*
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* -------DMA Register--------
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* DMA Status Reg.(+54H)
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*/
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#define PCI_MS_ABORT BIT(6)
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#define BLAST_COMPLETE BIT(5)
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#define SCSI_INTERRUPT BIT(4)
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#define DMA_XFER_DONE BIT(3)
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#define DMA_XFER_ABORT BIT(2)
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#define DMA_XFER_ERROR BIT(1)
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#define POWER_DOWN BIT(0)
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/*
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* -------DMA Register--------
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* DMA SCSI Bus and Ctrl.(+70H)
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* EN_INT_ON_PCI_ABORT
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*/
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/*
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*==========================================================
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* SCSI Chip register address offset
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*==========================================================
|
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*/
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#define CTCREG_LOW 0x00 /* (R) current transfer count register low */
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#define STCREG_LOW 0x00 /* (W) start transfer count register low */
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#define CTCREG_MID 0x04 /* (R) current transfer count register
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* middle */
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#define STCREG_MID 0x04 /* (W) start transfer count register middle */
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#define SCSIFIFOREG 0x08 /* (R/W) SCSI FIFO register */
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#define SCSICMDREG 0x0C /* (R/W) SCSI command register */
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#define SCSISTATREG 0x10 /* (R) SCSI status register */
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#define SCSIDESTIDREG 0x10 /* (W) SCSI destination ID register */
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#define INTSTATREG 0x14 /* (R) interrupt status register */
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#define SCSITIMEOUTREG 0x14 /* (W) SCSI timeout register */
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#define INTERNSTATREG 0x18 /* (R) internal state register */
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#define SYNCPERIOREG 0x18 /* (W) synchronous transfer period register */
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#define CURRENTFIFOREG 0x1C /* (R) current FIFO/internal state register */
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#define SYNCOFFREG 0x1C/* (W) synchronous transfer period register */
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#define CNTLREG1 0x20 /* (R/W) control register 1 */
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#define CLKFACTREG 0x24 /* (W) clock factor register */
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#define CNTLREG2 0x2C /* (R/W) control register 2 */
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#define CNTLREG3 0x30 /* (R/W) control register 3 */
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#define CNTLREG4 0x34 /* (R/W) control register 4 */
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#define CURTXTCNTREG 0x38 /* (R) current transfer count register
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* high/part-unique ID code */
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#define STCREG_HIGH 0x38 /* (W) Start current transfer count register
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* high */
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/*
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*********************************************************
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*
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* SCSI DMA register
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*
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*********************************************************
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*/
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#define DMA_Cmd 0x40 /* (R/W) command register */
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#define DMA_XferCnt 0x44 /* (R/W) starting transfer count */
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#define DMA_XferAddr 0x48 /* (R/W) starting Physical address */
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#define DMA_Wk_ByteCntr 0x4C /* ( R ) working byte counter */
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#define DMA_Wk_AddrCntr 0x50 /* ( R ) working address counter */
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#define DMA_Status 0x54 /* ( R ) status register */
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#define DMA_MDL_Addr 0x58 /* (R/W) starting memory descriptor list (MDL)
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* address */
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#define DMA_Wk_MDL_Cntr 0x5C /* ( R ) working MDL counter */
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#define DMA_ScsiBusCtrl 0x70 /* (bits R/W) SCSI BUS and control */
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/* ******************************************************* */
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#define am_target SCSISTATREG
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#define am_timeout INTSTATREG
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#define am_seq_step SYNCPERIOREG
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#define am_fifo_count SYNCOFFREG
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#define amd_read8(amd, port) \
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bus_space_read_1((amd)->tag, (amd)->bsh, port)
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#define amd_read16(amd, port) \
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bus_space_read_2((amd)->tag, (amd)->bsh, port)
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#define amd_read32(amd, port) \
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bus_space_read_4((amd)->tag, (amd)->bsh, port)
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#define amd_write8(amd, port, value) \
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bus_space_write_1((amd)->tag, (amd)->bsh, port, value)
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#define amd_write8_multi(amd, port, ptr, len) \
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bus_space_write_multi_1((amd)->tag, (amd)->bsh, port, ptr, len)
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#define amd_write16(amd, port, value) \
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bus_space_write_2((amd)->tag, (amd)->bsh, port, value)
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#define amd_write32(amd, port, value) \
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bus_space_write_4((amd)->tag, (amd)->bsh, port, value)
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#endif /* AMD_H */
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