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45d426a34e
mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
102 lines
3.6 KiB
C
102 lines
3.6 KiB
C
/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)ucontext.h 8.1 (Berkeley) 6/10/93
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* JNPR: ucontext.h,v 1.2 2007/08/09 11:23:32 katta
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* $FreeBSD$
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*/
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#ifndef _MACHINE_UCONTEXT_H_
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#define _MACHINE_UCONTEXT_H_
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#ifndef _LOCORE
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typedef struct __mcontext {
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/*
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* These fields must match the corresponding fields in struct
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* sigcontext which follow 'sc_mask'. That way we can support
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* struct sigcontext and ucontext_t at the same time.
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*/
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int mc_onstack; /* sigstack state to restore */
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register_t mc_pc; /* pc at time of signal */
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register_t mc_regs[32]; /* processor regs 0 to 31 */
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register_t sr; /* status register */
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register_t mullo, mulhi; /* mullo and mulhi registers... */
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int mc_fpused; /* fp has been used */
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f_register_t mc_fpregs[33]; /* fp regs 0 to 31 and csr */
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register_t mc_fpc_eir; /* fp exception instruction reg */
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int __spare__[8]; /* XXX reserved */
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} mcontext_t;
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#endif
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#define SZREG 4
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/* offsets into mcontext_t */
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#define UCTX_REG(x) (8 + (x)*SZREG)
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#define UCR_ZERO UCTX_REG(0)
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#define UCR_AT UCTX_REG(1)
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#define UCR_V0 UCTX_REG(2)
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#define UCR_V1 UCTX_REG(3)
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#define UCR_A0 UCTX_REG(4)
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#define UCR_A1 UCTX_REG(5)
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#define UCR_A2 UCTX_REG(6)
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#define UCR_A3 UCTX_REG(7)
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#define UCR_T0 UCTX_REG(8)
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#define UCR_T1 UCTX_REG(9)
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#define UCR_T2 UCTX_REG(10)
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#define UCR_T3 UCTX_REG(11)
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#define UCR_T4 UCTX_REG(12)
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#define UCR_T5 UCTX_REG(13)
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#define UCR_T6 UCTX_REG(14)
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#define UCR_T7 UCTX_REG(15)
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#define UCR_S0 UCTX_REG(16)
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#define UCR_S1 UCTX_REG(17)
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#define UCR_S2 UCTX_REG(18)
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#define UCR_S3 UCTX_REG(19)
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#define UCR_S4 UCTX_REG(20)
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#define UCR_S5 UCTX_REG(21)
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#define UCR_S6 UCTX_REG(22)
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#define UCR_S7 UCTX_REG(23)
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#define UCR_T8 UCTX_REG(24)
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#define UCR_T9 UCTX_REG(25)
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#define UCR_K0 UCTX_REG(26)
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#define UCR_K1 UCTX_REG(27)
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#define UCR_GP UCTX_REG(28)
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#define UCR_SP UCTX_REG(29)
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#define UCR_S8 UCTX_REG(30)
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#define UCR_RA UCTX_REG(31)
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#define UCR_SR UCTX_REG(32)
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#define UCR_MDLO UCTX_REG(33)
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#define UCR_MDHI UCTX_REG(34)
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#endif /* !_MACHINE_UCONTEXT_H_ */
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