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d78896e46f
Support for Pentium events was removed completely in e92a1350b5.
Don't bump .Dd where we are just removing xrefs.
Reviewed by: emaste
MFC after: 1 week
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D31423
233 lines
7.5 KiB
Groff
233 lines
7.5 KiB
Groff
.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara@gmail.com>
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd March 22, 2013
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.Dt PMC.HASWELLUC 3
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.Os
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.Sh NAME
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.Nm pmc.haswelluc
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.Nd uncore measurement events for
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.Tn Intel
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.Tn Haswell
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family CPUs
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.Sh LIBRARY
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.Lb libpmc
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.Sh SYNOPSIS
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.In pmc.h
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.Sh DESCRIPTION
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.Tn Intel
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.Tn "Haswell"
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CPUs contain PMCs conforming to version 3 of the
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.Tn Intel
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performance measurement architecture.
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These CPUs contain two classes of PMCs:
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.Bl -tag -width "Li PMC_CLASS_UCP"
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.It Li PMC_CLASS_UCF
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Fixed-function counters that count only one hardware event per counter.
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.It Li PMC_CLASS_UCP
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Programmable counters that may be configured to count one of a defined
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set of hardware events.
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.El
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.Pp
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The number of PMCs available in each class and their widths need to be
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determined at run time by calling
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.Xr pmc_cpuinfo 3 .
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.Pp
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Intel Haswell PMCs are documented in
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.Rs
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.%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
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.%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C"
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.%N "Order Number: 325462-045US"
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.%D January 2013
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.%Q "Intel Corporation"
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.Re
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.Ss HASWELL UNCORE FIXED FUNCTION PMCS
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These PMCs and their supported events are documented in
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.Xr pmc.ucf 3 .
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Not all CPUs in this family implement fixed-function counters.
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.Ss HASWELL UNCORE PROGRAMMABLE PMCS
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The programmable PMCs support the following capabilities:
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.Bl -column "PMC_CAP_INTERRUPT" "Support"
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.It Em Capability Ta Em Support
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.It PMC_CAP_CASCADE Ta \&No
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.It PMC_CAP_EDGE Ta Yes
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.It PMC_CAP_INTERRUPT Ta \&No
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.It PMC_CAP_INVERT Ta Yes
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.It PMC_CAP_READ Ta Yes
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.It PMC_CAP_PRECISE Ta \&No
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.It PMC_CAP_SYSTEM Ta \&No
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.It PMC_CAP_TAGGING Ta \&No
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.It PMC_CAP_THRESHOLD Ta Yes
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.It PMC_CAP_USER Ta \&No
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.It PMC_CAP_WRITE Ta Yes
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.El
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.Ss Event Qualifiers
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Event specifiers for these PMCs support the following common
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qualifiers:
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.Bl -tag -width indent
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.It Li cmask= Ns Ar value
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Configure the PMC to increment only if the number of configured
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events measured in a cycle is greater than or equal to
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.Ar value .
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.It Li edge
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Configure the PMC to count the number of de-asserted to asserted
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transitions of the conditions expressed by the other qualifiers.
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If specified, the counter will increment only once whenever a
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condition becomes true, irrespective of the number of clocks during
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which the condition remains true.
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.It Li inv
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Invert the sense of comparison when the
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.Dq Li cmask
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qualifier is present, making the counter increment when the number of
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events per cycle is less than the value specified by the
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.Dq Li cmask
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qualifier.
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.El
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.Ss Event Specifiers (Programmable PMCs)
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Haswell programmable PMCs support the following events:
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.Bl -tag -width indent
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.It Li UNC_CBO_XSNP_RESPONSE.MISS
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.Pq Event 22H , Umask 01H
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A snoop misses in some processor core.
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.It Li UNC_CBO_XSNP_RESPONSE.INVAL
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.Pq Event 22H , Umask 02H
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A snoop invalidates a non-modified line in some
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processor core.
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.It Li UNC_CBO_XSNP_RESPONSE.HIT
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.Pq Event 22H , Umask 04H
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A snoop hits a non-modified line in some processor
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core.
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.It Li UNC_CBO_XSNP_RESPONSE.HITM
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.Pq Event 22H , Umask 08H
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A snoop hits a modified line in some processor core.
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.It Li UNC_CBO_XSNP_RESPONSE.INVAL_M
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.Pq Event 22H , Umask 10H
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A snoop invalidates a modified line in some processor
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core.
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.It Li UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER
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.Pq Event 22H , Umask 20H
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Filter on cross-core snoops initiated by this Cbox due
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to external snoop request.
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.It Li UNC_CBO_XSNP_RESPONSE.XCORE_FILTER
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.Pq Event 22H , Umask 40H
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Filter on cross-core snoops initiated by this Cbox due
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to processor core memory request.
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.It Li UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER
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.Pq Event 22H , Umask 80H
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Filter on cross-core snoops initiated by this Cbox due
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to LLC eviction.
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.It Li UNC_CBO_CACHE_LOOKUP.M
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.Pq Event 34H , Umask 01H
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LLC lookup request that access cache and found line in
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M-state.
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.It Li UNC_CBO_CACHE_LOOKUP.ES
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.Pq Event 34H , Umask 06H
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LLC lookup request that access cache and found line in
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E or S state.
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.It Li UNC_CBO_CACHE_LOOKUP.I
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.Pq Event 34H , Umask 08H
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LLC lookup request that access cache and found line in
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I-state.
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.It Li UNC_CBO_CACHE_LOOKUP.READ_FILTER
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.Pq Event 34H , Umask 10H
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Filter on processor core initiated cacheable read
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requests.
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Must combine with at least one of 01H, 02H, 04H, 08H.
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.It Li UNC_CBO_CACHE_LOOKUP.WRITE_FILTER
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.Pq Event 34H , Umask 20H
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Filter on processor core initiated cacheable write requests.
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Must combine with at least one of 01H, 02H, 04H, 08H.
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.It Li UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER
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.Pq Event 34H , Umask 40H
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Filter on external snoop requests.
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Must combine with at least one of 01H, 02H, 04H, 08H.
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.It Li UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER
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.Pq Event 34H , Umask 80H
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Filter on any IRQ or IPQ initiated requests including
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uncacheable, non-coherent requests.
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Must combine with at least one of 01H, 02H, 04H, 08H.
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.It Li UNC_ARB_TRK_OCCUPANCY.ALL
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.Pq Event 80H , Umask 01H
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Counts cycles weighted by the number of requests
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waiting for data returning from the memory controller.
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Accounts for coherent and non-coherent requests
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initiated by IA cores, processor graphic units, or LLC.
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.It Li UNC_ARB_TRK_REQUEST.ALL
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.Pq Event 81H , Umask 01H
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Counts the number of coherent and in-coherent
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requests initiated by IA cores, processor graphic units,
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or LLC.
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.It Li UNC_ARB_TRK_REQUEST.WRITES
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.Pq Event 81H , Umask 20H
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Counts the number of allocated write entries, include
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full, partial, and LLC evictions.
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.It Li UNC_ARB_TRK_REQUEST.EVICTIONS
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.Pq Event 81H , Umask 80H
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Counts the number of LLC evictions allocated.
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.It Li UNC_ARB_COH , Umask TRK_OCCUPANCY.ALL
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.Pq Event 83H , Umask 01H
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Cycles weighted by number of requests pending in
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Coherency Tracker.
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.It Li UNC_ARB_COH , Umask TRK_REQUEST.ALL
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.Pq Event 84H , Umask 01H
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Number of requests allocated in Coherency Tracker.
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.El
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.Sh SEE ALSO
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.Xr pmc 3 ,
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.Xr pmc.atom 3 ,
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.Xr pmc.core 3 ,
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.Xr pmc.corei7 3 ,
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.Xr pmc.corei7uc 3 ,
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.Xr pmc.haswell 3 ,
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.Xr pmc.iaf 3 ,
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.sandybridge 3 ,
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.Xr pmc.sandybridgeuc 3 ,
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.Xr pmc.sandybridgexeon 3 ,
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.Xr pmc.soft 3 ,
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.Xr pmc.tsc 3 ,
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.Xr pmc.ucf 3 ,
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.Xr pmc.westmere 3 ,
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.Xr pmc.westmereuc 3 ,
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.Xr pmc_cpuinfo 3 ,
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.Xr pmclog 3 ,
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.Xr hwpmc 4
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.Sh HISTORY
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The
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.Nm pmc
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library first appeared in
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.Fx 6.0 .
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.Sh AUTHORS
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.An -nosplit
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The
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.Lb libpmc
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library was written by
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.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
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The support for the Haswell
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microarchitecture was added by
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.An Hiren Panchasara Aq Mt hiren.panchasara@gmail.com .
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