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d805b866fa
based on the HD64570 chip. Both the 1 and 2 port cards is supported. Line speeds of up to 2Mbps is possible. At this speed about 95% of the bandwidth is usable with 486DX processors. The standard FreeBSD sppp code is used for the link level layer. The default protocol used is PPP. The Cisco HDLC protocol can be used by adding "link2" to the ifconfig line in /etc/sysconfig or where ever ifconfig is run. At the moment only the X.21 interface is tested. The others may need tweaks to the clock selection code.
92 lines
4.0 KiB
C
92 lines
4.0 KiB
C
/*
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* Copyright (c) 1995 John Hay. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by [your name]
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* and [any other names deserving credit ]
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY [your name] AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id$
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*/
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#ifndef _IF_SRREGS_H_
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#define _IF_SRREGS_H_
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#define NCHAN 2 /* A HD64570 chip have 2 channels */
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#define SR_BUF_SIZ 512
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#define SR_TX_BLOCKS 2 /* Sepperate sets of tx buffers */
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#define SRC_IO_SIZ 0x10 /* Actually a lie. It uses a lot more. */
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#define SRC_WIN_SIZ 0x00004000
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#define SRC_WIN_MSK (SRC_WIN_SIZ - 1)
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#define SRC_WIN_SHFT 14
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#define SR_FLAGS_NCHAN_MSK 0x0000000F
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#define SR_FLAGS_0_CLK_MSK 0x00000030
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#define SR_FLAGS_0_EXT_CLK 0x00000000 /* External RX clock shared by TX */
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#define SR_FLAGS_0_EXT_SEP_CLK 0x00000010 /* Sepperate external clocks */
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#define SR_FLAGS_0_INT_CLK 0x00000020 /* Internal clock */
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#define SR_FLAGS_1_CLK_MSK 0x000000C0
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#define SR_FLAGS_1_EXT_CLK 0x00000000 /* External RX clock shared by TX */
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#define SR_FLAGS_1_EXT_SEP_CLK 0x00000040 /* Sepperate external clocks */
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#define SR_FLAGS_1_INT_CLK 0x00000080 /* Internal clock */
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#define SR_FLAGS_CLK_SHFT 4
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#define SR_FLAGS_CLK_CHAN_SHFT 2
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#define SR_FLAGS_EXT_CLK 0x00000000 /* External RX clock shared by TX */
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#define SR_FLAGS_EXT_SEP_CLK 0x00000001 /* Sepperate external clocks */
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#define SR_FLAGS_INT_CLK 0x00000002 /* Internal clock */
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#define SR_PCR 0x00 /* RW, PC Control Register */
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#define SR_BAR 0x02 /* RW, Base Address Register */
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#define SR_PSR 0x04 /* RW, Page Scan Register */
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#define SR_MCR 0x06 /* RW, Modem Control Register */
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#define SR_PCR_SCARUN 0x01 /* !Reset */
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#define SR_PCR_EN_VPM 0x02 /* Running above 1M */
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#define SR_PCR_MEM_WIN 0x04 /* Open memory window */
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#define SR_PCR_ISA16 0x08 /* 16 bit ISA mode */
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#define SR_PCR_16M_SEL 0xF0 /* A20-A23 Addresses */
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#define SR_PSR_PG_SEL 0x1F /* Page 0 - 31 select */
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#define SR_PG_MSK 0x1F
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#define SR_PSR_WIN_SIZ 0x60 /* Window size select */
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#define SR_PSR_WIN_16K 0x00
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#define SR_PSR_WIN_32K 0x20
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#define SR_PSR_WIN_64K 0x40
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#define SR_PSR_WIN_128K 0x60
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#define SR_PSR_EN_SCA_DMA 0x80 /* Enable the SCA DMA */
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#define SR_MCR_DTR0 0x01 /* Deactivate DTR0 */
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#define SR_MCR_DTR1 0x02 /* Deactivate DTR1 */
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#define SR_MCR_DSR0 0x04 /* DSR0 Status */
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#define SR_MCR_DSR1 0x08 /* DSR1 Status */
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#define SR_MCR_TE0 0x10 /* Enable RS422 TXD */
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#define SR_MCR_TE1 0x20 /* Enable RS422 TXD */
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#define SR_MCR_ETC0 0x40 /* Enable Ext Clock out */
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#define SR_MCR_ETC1 0x80 /* Enable Ext Clock out */
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#endif /* _IF_SRREGS_H_ */
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