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298 lines
7.0 KiB
C
298 lines
7.0 KiB
C
/*-
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* Copyright (c) 2011-2012 Semihalf
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef FSL_SDHC_H_
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#define FSL_SDHC_H_
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <sys/taskqueue.h>
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#include <machine/bus.h>
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#include <dev/mmc/bridge.h>
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#include <dev/mmc/mmcreg.h>
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#include <dev/mmc/mmcvar.h>
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#include <dev/mmc/mmcbrvar.h>
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#include "mmcbr_if.h"
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/*****************************************************************************
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* Private defines
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*****************************************************************************/
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struct slot {
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uint32_t clock;
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};
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struct fsl_sdhc_softc {
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device_t self;
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device_t child;
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bus_space_handle_t bsh;
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bus_space_tag_t bst;
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struct resource *mem_resource;
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int mem_rid;
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struct resource *irq_resource;
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int irq_rid;
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void *ihl;
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bus_dma_tag_t dma_tag;
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bus_dmamap_t dma_map;
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uint32_t* dma_mem;
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bus_addr_t dma_phys;
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struct mtx mtx;
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struct task card_detect_task;
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struct callout card_detect_callout;
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struct mmc_host mmc_host;
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struct slot slot;
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uint32_t bus_busy;
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uint32_t platform_clock;
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struct mmc_request *request;
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int data_done;
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int command_done;
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int use_dma;
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uint32_t* data_ptr;
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uint32_t data_offset;
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};
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#define FSL_SDHC_RESET_DELAY 50
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#define FSL_SDHC_BASE_CLOCK_DIV (2)
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#define FSL_SDHC_MAX_DIV (FSL_SDHC_BASE_CLOCK_DIV * 256 * 16)
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#define FSL_SDHC_MIN_DIV (FSL_SDHC_BASE_CLOCK_DIV * 2)
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#define FSL_SDHC_MAX_CLOCK (50000000)
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#define FSL_SDHC_MAX_BLOCK_COUNT (65535)
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#define FSL_SDHC_MAX_BLOCK_SIZE (4096)
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#define FSL_SDHC_FIFO_BUF_SIZE (64) /* Water-mark level. */
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#define FSL_SDHC_FIFO_BUF_WORDS (FSL_SDHC_FIFO_BUF_SIZE / 4)
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#define FSL_SDHC_DMA_SEGMENT_SIZE (1024)
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#define FSL_SDHC_DMA_ALIGNMENT (4)
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#define FSL_SDHC_DMA_BLOCK_SIZE FSL_SDHC_MAX_BLOCK_SIZE
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/*
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* Offsets of SD HC registers
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*/
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enum sdhc_reg_off {
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SDHC_DSADDR = 0x000,
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SDHC_BLKATTR = 0x004,
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SDHC_CMDARG = 0x008,
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SDHC_XFERTYP = 0x00c,
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SDHC_CMDRSP0 = 0x010,
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SDHC_CMDRSP1 = 0x014,
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SDHC_CMDRSP2 = 0x018,
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SDHC_CMDRSP3 = 0x01c,
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SDHC_DATPORT = 0x020,
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SDHC_PRSSTAT = 0x024,
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SDHC_PROCTL = 0x028,
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SDHC_SYSCTL = 0x02c,
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SDHC_IRQSTAT = 0x030,
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SDHC_IRQSTATEN = 0x034,
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SDHC_IRQSIGEN = 0x038,
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SDHC_AUTOC12ERR = 0x03c,
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SDHC_HOSTCAPBLT = 0x040,
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SDHC_WML = 0x044,
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SDHC_FEVT = 0x050,
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SDHC_HOSTVER = 0x0fc,
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SDHC_DCR = 0x40c
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};
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enum sysctl_bit {
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SYSCTL_INITA = 0x08000000,
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SYSCTL_RSTD = 0x04000000,
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SYSCTL_RSTC = 0x02000000,
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SYSCTL_RSTA = 0x01000000,
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SYSCTL_DTOCV = 0x000f0000,
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SYSCTL_SDCLKFS = 0x0000ff00,
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SYSCTL_DVS = 0x000000f0,
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SYSCTL_PEREN = 0x00000004,
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SYSCTL_HCKEN = 0x00000002,
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SYSCTL_IPGEN = 0x00000001
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};
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#define HEX_LEFT_SHIFT(x) (4 * x)
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enum sysctl_shift {
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SHIFT_DTOCV = HEX_LEFT_SHIFT(4),
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SHIFT_SDCLKFS = HEX_LEFT_SHIFT(2),
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SHIFT_DVS = HEX_LEFT_SHIFT(1)
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};
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enum proctl_bit {
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PROCTL_WECRM = 0x04000000,
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PROCTL_WECINS = 0x02000000,
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PROCTL_WECINT = 0x01000000,
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PROCTL_RWCTL = 0x00040000,
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PROCTL_CREQ = 0x00020000,
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PROCTL_SABGREQ = 0x00010000,
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PROCTL_CDSS = 0x00000080,
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PROCTL_CDTL = 0x00000040,
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PROCTL_EMODE = 0x00000030,
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PROCTL_D3CD = 0x00000008,
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PROCTL_DTW = 0x00000006
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};
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enum dtw {
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DTW_1 = 0x00000000,
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DTW_4 = 0x00000002,
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DTW_8 = 0x00000004
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};
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enum prsstat_bit {
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PRSSTAT_DLSL = 0xff000000,
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PRSSTAT_CLSL = 0x00800000,
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PRSSTAT_WPSPL = 0x00080000,
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PRSSTAT_CDPL = 0x00040000,
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PRSSTAT_CINS = 0x00010000,
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PRSSTAT_BREN = 0x00000800,
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PRSSTAT_BWEN = 0x00000400,
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PRSSTAT_RTA = 0x00000200,
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PRSSTAT_WTA = 0x00000100,
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PRSSTAT_SDOFF = 0x00000080,
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PRSSTAT_PEROFF = 0x00000040,
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PRSSTAT_HCKOFF = 0x00000020,
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PRSSTAT_IPGOFF = 0x00000010,
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PRSSTAT_DLA = 0x00000004,
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PRSSTAT_CDIHB = 0x00000002,
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PRSSTAT_CIHB = 0x00000001
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};
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enum irq_bits {
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IRQ_DMAE = 0x10000000,
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IRQ_AC12E = 0x01000000,
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IRQ_DEBE = 0x00400000,
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IRQ_DCE = 0x00200000,
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IRQ_DTOE = 0x00100000,
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IRQ_CIE = 0x00080000,
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IRQ_CEBE = 0x00040000,
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IRQ_CCE = 0x00020000,
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IRQ_CTOE = 0x00010000,
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IRQ_CINT = 0x00000100,
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IRQ_CRM = 0x00000080,
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IRQ_CINS = 0x00000040,
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IRQ_BRR = 0x00000020,
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IRQ_BWR = 0x00000010,
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IRQ_DINT = 0x00000008,
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IRQ_BGE = 0x00000004,
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IRQ_TC = 0x00000002,
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IRQ_CC = 0x00000001
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};
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enum irq_masks {
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IRQ_ERROR_DATA_MASK = IRQ_DMAE | IRQ_DEBE | IRQ_DCE | IRQ_DTOE,
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IRQ_ERROR_CMD_MASK = IRQ_AC12E | IRQ_CIE | IRQ_CTOE | IRQ_CCE |
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IRQ_CEBE
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};
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enum dcr_bits {
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DCR_PRI = 0x0000c000,
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DCR_SNOOP = 0x00000040,
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DCR_AHB2MAG_BYPASS = 0x00000020,
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DCR_RD_SAFE = 0x00000004,
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DCR_RD_PFE = 0x00000002,
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DCR_RD_PF_SIZE = 0x00000001
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};
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#define DCR_PRI_SHIFT (14)
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enum xfertyp_bits {
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XFERTYP_CMDINX = 0x3f000000,
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XFERTYP_CMDTYP = 0x00c00000,
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XFERTYP_DPSEL = 0x00200000,
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XFERTYP_CICEN = 0x00100000,
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XFERTYP_CCCEN = 0x00080000,
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XFERTYP_RSPTYP = 0x00030000,
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XFERTYP_MSBSEL = 0x00000020,
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XFERTYP_DTDSEL = 0x00000010,
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XFERTYP_AC12EN = 0x00000004,
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XFERTYP_BCEN = 0x00000002,
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XFERTYP_DMAEN = 0x00000001
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};
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#define CMDINX_SHIFT (24)
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enum xfertyp_cmdtyp {
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CMDTYP_NORMAL = 0x00000000,
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CMDYTP_SUSPEND = 0x00400000,
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CMDTYP_RESUME = 0x00800000,
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CMDTYP_ABORT = 0x00c00000
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};
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enum xfertyp_rsptyp {
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RSPTYP_NONE = 0x00000000,
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RSPTYP_136 = 0x00010000,
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RSPTYP_48 = 0x00020000,
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RSPTYP_48_BUSY = 0x00030000
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};
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enum blkattr_bits {
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BLKATTR_BLKSZE = 0x00001fff,
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BLKATTR_BLKCNT = 0xffff0000
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};
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#define BLKATTR_BLOCK_COUNT(x) (x << 16)
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enum wml_bits {
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WR_WML = 0x00ff0000,
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RD_WML = 0x000000ff,
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};
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enum sdhc_bit_mask {
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MASK_CLOCK_CONTROL = 0x0000ffff,
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MASK_IRQ_ALL = IRQ_DMAE | IRQ_AC12E | IRQ_DEBE | IRQ_DCE |
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IRQ_DTOE | IRQ_CIE | IRQ_CEBE | IRQ_CCE |
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IRQ_CTOE | IRQ_CINT | IRQ_CRM | IRQ_CINS |
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IRQ_BRR | IRQ_BWR | IRQ_DINT | IRQ_BGE |
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IRQ_TC | IRQ_CC,
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};
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enum sdhc_line {
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SDHC_DAT_LINE = 0x2,
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SDHC_CMD_LINE = 0x1
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};
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#endif /* FSL_SDHC_H_ */
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