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8ec87fc514
em revision 7.0.0: - Using driver devclass, seperate legacy (pre-pcie) code into a seperate source file. This will at least help protect against regression issues. It compiles along with em, and is transparent to end use, devices in each appear to be 'emX'. When using em in a modular form this also allows the legacy stuff to be defined out. - Add tx and rx rings as in igb, in the 82574 this becomes actual multiqueue for the first time (2 queues) while in other PCIE adapters its just make code cleaner. - Add RX mbuf handling logic that matches igb, this will eliminate packet drops due to temporary mbuf shortage. igb revision 1.9.3: - Following the ixgbe code, use a new approach in what was called 'get_buf', the routine now has been made independent of rxeof, it now does the update to the engine TDT register, this design allows temporary mbuf resources to become non-critical, not requiring a packet to be discarded, instead it just returns and does not increment the tail pointer. - With the above change it was also unnecessary to keep 'spare' maps around, since we do not have the discard issue. - Performance tweaks and improvements to the code also. MFC in a week
868 lines
23 KiB
C
868 lines
23 KiB
C
/******************************************************************************
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Copyright (c) 2001-2010, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#ifndef _E1000_HW_H_
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#define _E1000_HW_H_
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#include "e1000_osdep.h"
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#include "e1000_regs.h"
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#include "e1000_defines.h"
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struct e1000_hw;
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#define E1000_DEV_ID_82542 0x1000
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#define E1000_DEV_ID_82543GC_FIBER 0x1001
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#define E1000_DEV_ID_82543GC_COPPER 0x1004
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#define E1000_DEV_ID_82544EI_COPPER 0x1008
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#define E1000_DEV_ID_82544EI_FIBER 0x1009
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#define E1000_DEV_ID_82544GC_COPPER 0x100C
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#define E1000_DEV_ID_82544GC_LOM 0x100D
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#define E1000_DEV_ID_82540EM 0x100E
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#define E1000_DEV_ID_82540EM_LOM 0x1015
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#define E1000_DEV_ID_82540EP_LOM 0x1016
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#define E1000_DEV_ID_82540EP 0x1017
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#define E1000_DEV_ID_82540EP_LP 0x101E
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#define E1000_DEV_ID_82545EM_COPPER 0x100F
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#define E1000_DEV_ID_82545EM_FIBER 0x1011
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#define E1000_DEV_ID_82545GM_COPPER 0x1026
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#define E1000_DEV_ID_82545GM_FIBER 0x1027
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#define E1000_DEV_ID_82545GM_SERDES 0x1028
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#define E1000_DEV_ID_82546EB_COPPER 0x1010
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#define E1000_DEV_ID_82546EB_FIBER 0x1012
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#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
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#define E1000_DEV_ID_82546GB_COPPER 0x1079
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#define E1000_DEV_ID_82546GB_FIBER 0x107A
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#define E1000_DEV_ID_82546GB_SERDES 0x107B
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#define E1000_DEV_ID_82546GB_PCIE 0x108A
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#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
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#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
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#define E1000_DEV_ID_82541EI 0x1013
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#define E1000_DEV_ID_82541EI_MOBILE 0x1018
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#define E1000_DEV_ID_82541ER_LOM 0x1014
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#define E1000_DEV_ID_82541ER 0x1078
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#define E1000_DEV_ID_82541GI 0x1076
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#define E1000_DEV_ID_82541GI_LF 0x107C
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#define E1000_DEV_ID_82541GI_MOBILE 0x1077
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#define E1000_DEV_ID_82547EI 0x1019
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#define E1000_DEV_ID_82547EI_MOBILE 0x101A
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#define E1000_DEV_ID_82547GI 0x1075
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#define E1000_DEV_ID_82571EB_COPPER 0x105E
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#define E1000_DEV_ID_82571EB_FIBER 0x105F
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#define E1000_DEV_ID_82571EB_SERDES 0x1060
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#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
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#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
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#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
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#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
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#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
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#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
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#define E1000_DEV_ID_82572EI_COPPER 0x107D
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#define E1000_DEV_ID_82572EI_FIBER 0x107E
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#define E1000_DEV_ID_82572EI_SERDES 0x107F
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#define E1000_DEV_ID_82572EI 0x10B9
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#define E1000_DEV_ID_82573E 0x108B
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#define E1000_DEV_ID_82573E_IAMT 0x108C
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#define E1000_DEV_ID_82573L 0x109A
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#define E1000_DEV_ID_82574L 0x10D3
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#define E1000_DEV_ID_82574LA 0x10F6
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#define E1000_DEV_ID_82583V 0x150C
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#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
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#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
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#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
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#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
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#define E1000_DEV_ID_ICH8_82567V_3 0x1501
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#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
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#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
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#define E1000_DEV_ID_ICH8_IGP_C 0x104B
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#define E1000_DEV_ID_ICH8_IFE 0x104C
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#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
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#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
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#define E1000_DEV_ID_ICH8_IGP_M 0x104D
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#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
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#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
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#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
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#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
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#define E1000_DEV_ID_ICH9_BM 0x10E5
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#define E1000_DEV_ID_ICH9_IGP_C 0x294C
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#define E1000_DEV_ID_ICH9_IFE 0x10C0
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#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
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#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
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#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
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#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
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#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
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#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
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#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
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#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
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#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
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#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
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#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
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#define E1000_DEV_ID_82576 0x10C9
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#define E1000_DEV_ID_82576_FIBER 0x10E6
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#define E1000_DEV_ID_82576_SERDES 0x10E7
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#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
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#define E1000_DEV_ID_82576_NS 0x150A
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#define E1000_DEV_ID_82576_NS_SERDES 0x1518
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#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
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#define E1000_DEV_ID_82575EB_COPPER 0x10A7
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#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
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#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
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#define E1000_DEV_ID_82575GB_QUAD_COPPER_PM 0x10E2
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#define E1000_DEV_ID_82580_COPPER 0x150E
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#define E1000_DEV_ID_82580_FIBER 0x150F
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#define E1000_DEV_ID_82580_SERDES 0x1510
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#define E1000_DEV_ID_82580_SGMII 0x1511
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#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
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#define E1000_REVISION_0 0
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#define E1000_REVISION_1 1
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#define E1000_REVISION_2 2
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#define E1000_REVISION_3 3
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#define E1000_REVISION_4 4
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#define E1000_FUNC_0 0
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#define E1000_FUNC_1 1
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#define E1000_FUNC_2 2
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#define E1000_FUNC_3 3
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#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
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#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
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#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
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#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
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enum e1000_mac_type {
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e1000_undefined = 0,
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e1000_82542,
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e1000_82543,
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e1000_82544,
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e1000_82540,
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e1000_82545,
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e1000_82545_rev_3,
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e1000_82546,
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e1000_82546_rev_3,
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e1000_82541,
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e1000_82541_rev_2,
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e1000_82547,
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e1000_82547_rev_2,
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e1000_82571,
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e1000_82572,
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e1000_82573,
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e1000_82574,
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e1000_82583,
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e1000_80003es2lan,
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e1000_ich8lan,
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e1000_ich9lan,
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e1000_ich10lan,
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e1000_pchlan,
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e1000_82575,
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e1000_82576,
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e1000_82580,
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e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
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};
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enum e1000_media_type {
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e1000_media_type_unknown = 0,
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e1000_media_type_copper = 1,
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e1000_media_type_fiber = 2,
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e1000_media_type_internal_serdes = 3,
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e1000_num_media_types
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};
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enum e1000_nvm_type {
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e1000_nvm_unknown = 0,
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e1000_nvm_none,
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e1000_nvm_eeprom_spi,
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e1000_nvm_eeprom_microwire,
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e1000_nvm_flash_hw,
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e1000_nvm_flash_sw
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};
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enum e1000_nvm_override {
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e1000_nvm_override_none = 0,
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e1000_nvm_override_spi_small,
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e1000_nvm_override_spi_large,
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e1000_nvm_override_microwire_small,
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e1000_nvm_override_microwire_large
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};
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enum e1000_phy_type {
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e1000_phy_unknown = 0,
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e1000_phy_none,
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e1000_phy_m88,
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e1000_phy_igp,
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e1000_phy_igp_2,
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e1000_phy_gg82563,
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e1000_phy_igp_3,
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e1000_phy_ife,
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e1000_phy_bm,
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e1000_phy_82578,
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e1000_phy_82577,
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e1000_phy_82580,
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e1000_phy_vf,
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};
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enum e1000_bus_type {
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e1000_bus_type_unknown = 0,
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e1000_bus_type_pci,
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e1000_bus_type_pcix,
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e1000_bus_type_pci_express,
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e1000_bus_type_reserved
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};
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enum e1000_bus_speed {
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e1000_bus_speed_unknown = 0,
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e1000_bus_speed_33,
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e1000_bus_speed_66,
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e1000_bus_speed_100,
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e1000_bus_speed_120,
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e1000_bus_speed_133,
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e1000_bus_speed_2500,
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e1000_bus_speed_5000,
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e1000_bus_speed_reserved
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};
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enum e1000_bus_width {
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e1000_bus_width_unknown = 0,
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e1000_bus_width_pcie_x1,
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e1000_bus_width_pcie_x2,
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e1000_bus_width_pcie_x4 = 4,
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e1000_bus_width_pcie_x8 = 8,
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e1000_bus_width_32,
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e1000_bus_width_64,
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e1000_bus_width_reserved
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};
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enum e1000_1000t_rx_status {
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e1000_1000t_rx_status_not_ok = 0,
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e1000_1000t_rx_status_ok,
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e1000_1000t_rx_status_undefined = 0xFF
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};
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enum e1000_rev_polarity {
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e1000_rev_polarity_normal = 0,
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e1000_rev_polarity_reversed,
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e1000_rev_polarity_undefined = 0xFF
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};
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enum e1000_fc_mode {
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e1000_fc_none = 0,
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e1000_fc_rx_pause,
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e1000_fc_tx_pause,
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e1000_fc_full,
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e1000_fc_default = 0xFF
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};
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enum e1000_ffe_config {
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e1000_ffe_config_enabled = 0,
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e1000_ffe_config_active,
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e1000_ffe_config_blocked
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};
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enum e1000_dsp_config {
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e1000_dsp_config_disabled = 0,
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e1000_dsp_config_enabled,
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e1000_dsp_config_activated,
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e1000_dsp_config_undefined = 0xFF
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};
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enum e1000_ms_type {
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e1000_ms_hw_default = 0,
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e1000_ms_force_master,
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e1000_ms_force_slave,
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e1000_ms_auto
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};
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enum e1000_smart_speed {
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e1000_smart_speed_default = 0,
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e1000_smart_speed_on,
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e1000_smart_speed_off
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};
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enum e1000_serdes_link_state {
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e1000_serdes_link_down = 0,
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e1000_serdes_link_autoneg_progress,
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e1000_serdes_link_autoneg_complete,
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e1000_serdes_link_forced_up
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};
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/* Receive Descriptor */
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struct e1000_rx_desc {
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__le64 buffer_addr; /* Address of the descriptor's data buffer */
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__le16 length; /* Length of data DMAed into data buffer */
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__le16 csum; /* Packet checksum */
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u8 status; /* Descriptor status */
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u8 errors; /* Descriptor Errors */
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__le16 special;
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};
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/* Receive Descriptor - Extended */
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union e1000_rx_desc_extended {
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struct {
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__le64 buffer_addr;
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__le64 reserved;
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} read;
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struct {
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struct {
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__le32 mrq; /* Multiple Rx Queues */
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union {
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__le32 rss; /* RSS Hash */
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struct {
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__le16 ip_id; /* IP id */
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__le16 csum; /* Packet Checksum */
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} csum_ip;
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} hi_dword;
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} lower;
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struct {
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__le32 status_error; /* ext status/error */
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__le16 length;
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__le16 vlan; /* VLAN tag */
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} upper;
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} wb; /* writeback */
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};
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#define MAX_PS_BUFFERS 4
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/* Receive Descriptor - Packet Split */
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union e1000_rx_desc_packet_split {
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struct {
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/* one buffer for protocol header(s), three data buffers */
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__le64 buffer_addr[MAX_PS_BUFFERS];
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} read;
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struct {
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struct {
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__le32 mrq; /* Multiple Rx Queues */
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union {
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__le32 rss; /* RSS Hash */
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struct {
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__le16 ip_id; /* IP id */
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__le16 csum; /* Packet Checksum */
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} csum_ip;
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} hi_dword;
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} lower;
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struct {
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__le32 status_error; /* ext status/error */
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__le16 length0; /* length of buffer 0 */
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__le16 vlan; /* VLAN tag */
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} middle;
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struct {
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__le16 header_status;
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__le16 length[3]; /* length of buffers 1-3 */
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} upper;
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__le64 reserved;
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} wb; /* writeback */
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};
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/* Transmit Descriptor */
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struct e1000_tx_desc {
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__le64 buffer_addr; /* Address of the descriptor's data buffer */
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union {
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__le32 data;
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struct {
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__le16 length; /* Data buffer length */
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u8 cso; /* Checksum offset */
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u8 cmd; /* Descriptor control */
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} flags;
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} lower;
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union {
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__le32 data;
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struct {
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u8 status; /* Descriptor status */
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u8 css; /* Checksum start */
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__le16 special;
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} fields;
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} upper;
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};
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/* Offload Context Descriptor */
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struct e1000_context_desc {
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union {
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__le32 ip_config;
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struct {
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u8 ipcss; /* IP checksum start */
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u8 ipcso; /* IP checksum offset */
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__le16 ipcse; /* IP checksum end */
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} ip_fields;
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} lower_setup;
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union {
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__le32 tcp_config;
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struct {
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u8 tucss; /* TCP checksum start */
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u8 tucso; /* TCP checksum offset */
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__le16 tucse; /* TCP checksum end */
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} tcp_fields;
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} upper_setup;
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__le32 cmd_and_length;
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union {
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__le32 data;
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struct {
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u8 status; /* Descriptor status */
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u8 hdr_len; /* Header length */
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__le16 mss; /* Maximum segment size */
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} fields;
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|
} tcp_seg_setup;
|
|
};
|
|
|
|
/* Offload data descriptor */
|
|
struct e1000_data_desc {
|
|
__le64 buffer_addr; /* Address of the descriptor's buffer address */
|
|
union {
|
|
__le32 data;
|
|
struct {
|
|
__le16 length; /* Data buffer length */
|
|
u8 typ_len_ext;
|
|
u8 cmd;
|
|
} flags;
|
|
} lower;
|
|
union {
|
|
__le32 data;
|
|
struct {
|
|
u8 status; /* Descriptor status */
|
|
u8 popts; /* Packet Options */
|
|
__le16 special;
|
|
} fields;
|
|
} upper;
|
|
};
|
|
|
|
/* Statistics counters collected by the MAC */
|
|
struct e1000_hw_stats {
|
|
u64 crcerrs;
|
|
u64 algnerrc;
|
|
u64 symerrs;
|
|
u64 rxerrc;
|
|
u64 mpc;
|
|
u64 scc;
|
|
u64 ecol;
|
|
u64 mcc;
|
|
u64 latecol;
|
|
u64 colc;
|
|
u64 dc;
|
|
u64 tncrs;
|
|
u64 sec;
|
|
u64 cexterr;
|
|
u64 rlec;
|
|
u64 xonrxc;
|
|
u64 xontxc;
|
|
u64 xoffrxc;
|
|
u64 xofftxc;
|
|
u64 fcruc;
|
|
u64 prc64;
|
|
u64 prc127;
|
|
u64 prc255;
|
|
u64 prc511;
|
|
u64 prc1023;
|
|
u64 prc1522;
|
|
u64 gprc;
|
|
u64 bprc;
|
|
u64 mprc;
|
|
u64 gptc;
|
|
u64 gorc;
|
|
u64 gotc;
|
|
u64 rnbc;
|
|
u64 ruc;
|
|
u64 rfc;
|
|
u64 roc;
|
|
u64 rjc;
|
|
u64 mgprc;
|
|
u64 mgpdc;
|
|
u64 mgptc;
|
|
u64 tor;
|
|
u64 tot;
|
|
u64 tpr;
|
|
u64 tpt;
|
|
u64 ptc64;
|
|
u64 ptc127;
|
|
u64 ptc255;
|
|
u64 ptc511;
|
|
u64 ptc1023;
|
|
u64 ptc1522;
|
|
u64 mptc;
|
|
u64 bptc;
|
|
u64 tsctc;
|
|
u64 tsctfc;
|
|
u64 iac;
|
|
u64 icrxptc;
|
|
u64 icrxatc;
|
|
u64 ictxptc;
|
|
u64 ictxatc;
|
|
u64 ictxqec;
|
|
u64 ictxqmtc;
|
|
u64 icrxdmtc;
|
|
u64 icrxoc;
|
|
u64 cbtmpc;
|
|
u64 htdpmc;
|
|
u64 cbrdpc;
|
|
u64 cbrmpc;
|
|
u64 rpthc;
|
|
u64 hgptc;
|
|
u64 htcbdpc;
|
|
u64 hgorc;
|
|
u64 hgotc;
|
|
u64 lenerrs;
|
|
u64 scvpc;
|
|
u64 hrmpc;
|
|
u64 doosync;
|
|
};
|
|
|
|
|
|
struct e1000_phy_stats {
|
|
u32 idle_errors;
|
|
u32 receive_errors;
|
|
};
|
|
|
|
struct e1000_host_mng_dhcp_cookie {
|
|
u32 signature;
|
|
u8 status;
|
|
u8 reserved0;
|
|
u16 vlan_id;
|
|
u32 reserved1;
|
|
u16 reserved2;
|
|
u8 reserved3;
|
|
u8 checksum;
|
|
};
|
|
|
|
/* Host Interface "Rev 1" */
|
|
struct e1000_host_command_header {
|
|
u8 command_id;
|
|
u8 command_length;
|
|
u8 command_options;
|
|
u8 checksum;
|
|
};
|
|
|
|
#define E1000_HI_MAX_DATA_LENGTH 252
|
|
struct e1000_host_command_info {
|
|
struct e1000_host_command_header command_header;
|
|
u8 command_data[E1000_HI_MAX_DATA_LENGTH];
|
|
};
|
|
|
|
/* Host Interface "Rev 2" */
|
|
struct e1000_host_mng_command_header {
|
|
u8 command_id;
|
|
u8 checksum;
|
|
u16 reserved1;
|
|
u16 reserved2;
|
|
u16 command_length;
|
|
};
|
|
|
|
#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
|
|
struct e1000_host_mng_command_info {
|
|
struct e1000_host_mng_command_header command_header;
|
|
u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
|
|
};
|
|
|
|
#include "e1000_mac.h"
|
|
#include "e1000_phy.h"
|
|
#include "e1000_nvm.h"
|
|
#include "e1000_manage.h"
|
|
|
|
struct e1000_mac_operations {
|
|
/* Function pointers for the MAC. */
|
|
s32 (*init_params)(struct e1000_hw *);
|
|
s32 (*id_led_init)(struct e1000_hw *);
|
|
s32 (*blink_led)(struct e1000_hw *);
|
|
s32 (*check_for_link)(struct e1000_hw *);
|
|
bool (*check_mng_mode)(struct e1000_hw *hw);
|
|
s32 (*cleanup_led)(struct e1000_hw *);
|
|
void (*clear_hw_cntrs)(struct e1000_hw *);
|
|
void (*clear_vfta)(struct e1000_hw *);
|
|
s32 (*get_bus_info)(struct e1000_hw *);
|
|
void (*set_lan_id)(struct e1000_hw *);
|
|
s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
|
|
s32 (*led_on)(struct e1000_hw *);
|
|
s32 (*led_off)(struct e1000_hw *);
|
|
void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
|
|
s32 (*reset_hw)(struct e1000_hw *);
|
|
s32 (*init_hw)(struct e1000_hw *);
|
|
void (*shutdown_serdes)(struct e1000_hw *);
|
|
void (*power_up_serdes)(struct e1000_hw *);
|
|
s32 (*setup_link)(struct e1000_hw *);
|
|
s32 (*setup_physical_interface)(struct e1000_hw *);
|
|
s32 (*setup_led)(struct e1000_hw *);
|
|
void (*write_vfta)(struct e1000_hw *, u32, u32);
|
|
void (*config_collision_dist)(struct e1000_hw *);
|
|
void (*rar_set)(struct e1000_hw *, u8*, u32);
|
|
s32 (*read_mac_addr)(struct e1000_hw *);
|
|
s32 (*validate_mdi_setting)(struct e1000_hw *);
|
|
s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
|
|
s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
|
|
struct e1000_host_mng_command_header*);
|
|
s32 (*mng_enable_host_if)(struct e1000_hw *);
|
|
s32 (*wait_autoneg)(struct e1000_hw *);
|
|
};
|
|
|
|
struct e1000_phy_operations {
|
|
s32 (*init_params)(struct e1000_hw *);
|
|
s32 (*acquire)(struct e1000_hw *);
|
|
s32 (*cfg_on_link_up)(struct e1000_hw *);
|
|
s32 (*check_polarity)(struct e1000_hw *);
|
|
s32 (*check_reset_block)(struct e1000_hw *);
|
|
s32 (*commit)(struct e1000_hw *);
|
|
s32 (*force_speed_duplex)(struct e1000_hw *);
|
|
s32 (*get_cfg_done)(struct e1000_hw *hw);
|
|
s32 (*get_cable_length)(struct e1000_hw *);
|
|
s32 (*get_info)(struct e1000_hw *);
|
|
s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
|
|
s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
|
|
void (*release)(struct e1000_hw *);
|
|
s32 (*reset)(struct e1000_hw *);
|
|
s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
|
|
s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
|
|
s32 (*write_reg)(struct e1000_hw *, u32, u16);
|
|
s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
|
|
void (*power_up)(struct e1000_hw *);
|
|
void (*power_down)(struct e1000_hw *);
|
|
};
|
|
|
|
struct e1000_nvm_operations {
|
|
s32 (*init_params)(struct e1000_hw *);
|
|
s32 (*acquire)(struct e1000_hw *);
|
|
s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
|
|
void (*release)(struct e1000_hw *);
|
|
void (*reload)(struct e1000_hw *);
|
|
s32 (*update)(struct e1000_hw *);
|
|
s32 (*valid_led_default)(struct e1000_hw *, u16 *);
|
|
s32 (*validate)(struct e1000_hw *);
|
|
s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
|
|
};
|
|
|
|
struct e1000_mac_info {
|
|
struct e1000_mac_operations ops;
|
|
u8 addr[6];
|
|
u8 perm_addr[6];
|
|
|
|
enum e1000_mac_type type;
|
|
|
|
u32 collision_delta;
|
|
u32 ledctl_default;
|
|
u32 ledctl_mode1;
|
|
u32 ledctl_mode2;
|
|
u32 mc_filter_type;
|
|
u32 tx_packet_delta;
|
|
u32 txcw;
|
|
|
|
u16 current_ifs_val;
|
|
u16 ifs_max_val;
|
|
u16 ifs_min_val;
|
|
u16 ifs_ratio;
|
|
u16 ifs_step_size;
|
|
u16 mta_reg_count;
|
|
u16 uta_reg_count;
|
|
|
|
/* Maximum size of the MTA register table in all supported adapters */
|
|
#define MAX_MTA_REG 128
|
|
u32 mta_shadow[MAX_MTA_REG];
|
|
u16 rar_entry_count;
|
|
|
|
u8 forced_speed_duplex;
|
|
|
|
bool adaptive_ifs;
|
|
bool has_fwsm;
|
|
bool arc_subsystem_valid;
|
|
bool asf_firmware_present;
|
|
bool autoneg;
|
|
bool autoneg_failed;
|
|
bool get_link_status;
|
|
bool in_ifs_mode;
|
|
bool report_tx_early;
|
|
enum e1000_serdes_link_state serdes_link_state;
|
|
bool serdes_has_link;
|
|
bool tx_pkt_filtering;
|
|
};
|
|
|
|
struct e1000_phy_info {
|
|
struct e1000_phy_operations ops;
|
|
enum e1000_phy_type type;
|
|
|
|
enum e1000_1000t_rx_status local_rx;
|
|
enum e1000_1000t_rx_status remote_rx;
|
|
enum e1000_ms_type ms_type;
|
|
enum e1000_ms_type original_ms_type;
|
|
enum e1000_rev_polarity cable_polarity;
|
|
enum e1000_smart_speed smart_speed;
|
|
|
|
u32 addr;
|
|
u32 id;
|
|
u32 reset_delay_us; /* in usec */
|
|
u32 revision;
|
|
|
|
enum e1000_media_type media_type;
|
|
|
|
u16 autoneg_advertised;
|
|
u16 autoneg_mask;
|
|
u16 cable_length;
|
|
u16 max_cable_length;
|
|
u16 min_cable_length;
|
|
|
|
u8 mdix;
|
|
|
|
bool disable_polarity_correction;
|
|
bool is_mdix;
|
|
bool polarity_correction;
|
|
bool reset_disable;
|
|
bool speed_downgraded;
|
|
bool autoneg_wait_to_complete;
|
|
};
|
|
|
|
struct e1000_nvm_info {
|
|
struct e1000_nvm_operations ops;
|
|
enum e1000_nvm_type type;
|
|
enum e1000_nvm_override override;
|
|
|
|
u32 flash_bank_size;
|
|
u32 flash_base_addr;
|
|
|
|
u16 word_size;
|
|
u16 delay_usec;
|
|
u16 address_bits;
|
|
u16 opcode_bits;
|
|
u16 page_size;
|
|
};
|
|
|
|
struct e1000_bus_info {
|
|
enum e1000_bus_type type;
|
|
enum e1000_bus_speed speed;
|
|
enum e1000_bus_width width;
|
|
|
|
u16 func;
|
|
u16 pci_cmd_word;
|
|
};
|
|
|
|
struct e1000_fc_info {
|
|
u32 high_water; /* Flow control high-water mark */
|
|
u32 low_water; /* Flow control low-water mark */
|
|
u16 pause_time; /* Flow control pause timer */
|
|
bool send_xon; /* Flow control send XON */
|
|
bool strict_ieee; /* Strict IEEE mode */
|
|
enum e1000_fc_mode current_mode; /* FC mode in effect */
|
|
enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
|
|
};
|
|
|
|
struct e1000_dev_spec_82541 {
|
|
enum e1000_dsp_config dsp_config;
|
|
enum e1000_ffe_config ffe_config;
|
|
u16 spd_default;
|
|
bool phy_init_script;
|
|
};
|
|
|
|
struct e1000_dev_spec_82542 {
|
|
bool dma_fairness;
|
|
};
|
|
|
|
struct e1000_dev_spec_82543 {
|
|
u32 tbi_compatibility;
|
|
bool dma_fairness;
|
|
bool init_phy_disabled;
|
|
};
|
|
|
|
struct e1000_dev_spec_82571 {
|
|
bool laa_is_present;
|
|
u32 smb_counter;
|
|
};
|
|
|
|
struct e1000_dev_spec_80003es2lan {
|
|
bool mdic_wa_enable;
|
|
};
|
|
|
|
struct e1000_shadow_ram {
|
|
u16 value;
|
|
bool modified;
|
|
};
|
|
|
|
#define E1000_SHADOW_RAM_WORDS 2048
|
|
|
|
struct e1000_dev_spec_ich8lan {
|
|
bool kmrn_lock_loss_workaround_enabled;
|
|
struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
|
|
E1000_MUTEX nvm_mutex;
|
|
E1000_MUTEX swflag_mutex;
|
|
bool nvm_k1_enabled;
|
|
};
|
|
|
|
struct e1000_dev_spec_82575 {
|
|
bool sgmii_active;
|
|
bool global_device_reset;
|
|
};
|
|
|
|
struct e1000_dev_spec_vf {
|
|
u32 vf_number;
|
|
u32 v2p_mailbox;
|
|
};
|
|
|
|
|
|
struct e1000_hw {
|
|
void *back;
|
|
|
|
u8 *hw_addr;
|
|
u8 *flash_address;
|
|
unsigned long io_base;
|
|
|
|
struct e1000_mac_info mac;
|
|
struct e1000_fc_info fc;
|
|
struct e1000_phy_info phy;
|
|
struct e1000_nvm_info nvm;
|
|
struct e1000_bus_info bus;
|
|
struct e1000_host_mng_dhcp_cookie mng_cookie;
|
|
|
|
union {
|
|
struct e1000_dev_spec_82541 _82541;
|
|
struct e1000_dev_spec_82542 _82542;
|
|
struct e1000_dev_spec_82543 _82543;
|
|
struct e1000_dev_spec_82571 _82571;
|
|
struct e1000_dev_spec_80003es2lan _80003es2lan;
|
|
struct e1000_dev_spec_ich8lan ich8lan;
|
|
struct e1000_dev_spec_82575 _82575;
|
|
struct e1000_dev_spec_vf vf;
|
|
} dev_spec;
|
|
|
|
u16 device_id;
|
|
u16 subsystem_vendor_id;
|
|
u16 subsystem_device_id;
|
|
u16 vendor_id;
|
|
|
|
u8 revision_id;
|
|
};
|
|
|
|
#include "e1000_82541.h"
|
|
#include "e1000_82543.h"
|
|
#include "e1000_82571.h"
|
|
#include "e1000_80003es2lan.h"
|
|
#include "e1000_ich8lan.h"
|
|
#include "e1000_82575.h"
|
|
|
|
/* These functions must be implemented by drivers */
|
|
void e1000_pci_clear_mwi(struct e1000_hw *hw);
|
|
void e1000_pci_set_mwi(struct e1000_hw *hw);
|
|
s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
|
|
s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
|
|
void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
|
|
void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
|
|
|
|
#endif
|