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215 lines
6.7 KiB
ArmAsm
215 lines
6.7 KiB
ArmAsm
/* $NetBSD: cpufunc_asm_armv5_ec.S,v 1.1 2007/01/06 00:50:54 christos Exp $ */
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/*
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* Copyright (c) 2002, 2005 ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* ARMv5 assembly functions for manipulating caches.
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* These routines can be used by any core that supports both the set/index
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* operations and the test and clean operations for efficiently cleaning the
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* entire DCache. If a core does not have the test and clean operations, but
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* does have the set/index operations, use the routines in cpufunc_asm_armv5.S.
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* This source was derived from that file.
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*/
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#include <machine/asm.h>
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__FBSDID("$FreeBSD$");
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/*
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* Functions to set the MMU Translation Table Base register
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*
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* We need to clean and flush the cache as it uses virtual
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* addresses that are about to change.
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*/
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ENTRY(armv5_ec_setttb)
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/*
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* Some other ARM ports save registers on the stack, call the
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* idcache_wbinv_all function and then restore the registers from the
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* stack before setting the TTB. I observed that this caused a
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* problem when the old and new translation table entries' buffering
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* bits were different. If I saved the registers in other registers
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* or invalidated the caches when I returned from idcache_wbinv_all,
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* it worked fine. If not, I ended up executing at an invalid PC.
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* For armv5_ec_settb, the idcache_wbinv_all is simple enough, I just
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* do it directly and entirely avoid the problem.
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*/
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mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
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1: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */
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bne 1b /* More to do? */
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
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mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
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RET
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END(armv5_ec_setttb)
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/*
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* Cache operations. For the entire cache we use the enhanced cache
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* operations.
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*/
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ENTRY_NP(armv5_ec_icache_sync_range)
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ldr ip, .Larmv5_ec_line_size
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cmp r1, #0x4000
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bcs .Larmv5_ec_icache_sync_all
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ldr ip, [ip]
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sub r1, r1, #1 /* Don't overrun */
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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1:
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mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
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mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
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add r0, r0, ip
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subs r1, r1, ip
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bpl 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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.Larmv5_ec_icache_sync_all:
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/*
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* We assume that the code here can never be out of sync with the
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* dcache, so that we can safely flush the Icache and fall through
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* into the Dcache cleaning code.
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*/
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mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
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/* Fall through to clean Dcache. */
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.Larmv5_ec_dcache_wb:
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1:
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mrc p15, 0, APSR_nzcv, c7, c10, 3 /* Test and clean (don't invalidate) */
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bne 1b /* More to do? */
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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END(armv5_ec_icache_sync_range)
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.Larmv5_ec_line_size:
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.word _C_LABEL(arm_pdcache_line_size)
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ENTRY(armv5_ec_dcache_wb_range)
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ldr ip, .Larmv5_ec_line_size
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cmp r1, #0x4000
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bcs .Larmv5_ec_dcache_wb
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ldr ip, [ip]
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sub r1, r1, #1 /* Don't overrun */
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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1:
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mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
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add r0, r0, ip
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subs r1, r1, ip
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bpl 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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END(armv5_ec_dcache_wb_range)
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ENTRY(armv5_ec_dcache_wbinv_range)
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ldr ip, .Larmv5_ec_line_size
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cmp r1, #0x4000
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bcs .Larmv5_ec_dcache_wbinv_all
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ldr ip, [ip]
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sub r1, r1, #1 /* Don't overrun */
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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1:
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mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
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add r0, r0, ip
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subs r1, r1, ip
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bpl 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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END(armv5_ec_dcache_wbinv_range)
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/*
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* Note, we must not invalidate everything. If the range is too big we
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* must use wb-inv of the entire cache.
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*/
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ENTRY(armv5_ec_dcache_inv_range)
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ldr ip, .Larmv5_ec_line_size
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cmp r1, #0x4000
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bcs .Larmv5_ec_dcache_wbinv_all
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ldr ip, [ip]
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sub r1, r1, #1 /* Don't overrun */
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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1:
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mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
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add r0, r0, ip
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subs r1, r1, ip
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bpl 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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END(armv5_ec_dcache_inv_range)
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ENTRY(armv5_ec_idcache_wbinv_range)
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ldr ip, .Larmv5_ec_line_size
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cmp r1, #0x4000
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bcs .Larmv5_ec_idcache_wbinv_all
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ldr ip, [ip]
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sub r1, r1, #1 /* Don't overrun */
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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1:
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mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
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mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
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add r0, r0, ip
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subs r1, r1, ip
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bpl 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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END(armv5_ec_idcache_wbinv_range)
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ENTRY_NP(armv5_ec_idcache_wbinv_all)
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.Larmv5_ec_idcache_wbinv_all:
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/*
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* We assume that the code here can never be out of sync with the
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* dcache, so that we can safely flush the Icache and fall through
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* into the Dcache purging code.
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*/
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mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
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/* Fall through to purge Dcache. */
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END(armv5_ec_idcache_wbinv_all)
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ENTRY(armv5_ec_dcache_wbinv_all)
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.Larmv5_ec_dcache_wbinv_all:
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1: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */
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bne 1b /* More to do? */
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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END(armv5_ec_dcache_wbinv_all)
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