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bf1e897425
value on entry and exit. This isn't as easy as it sounds because when we recursively trap or interrupt, we have to avoid duplicating the swapgs instruction or we end up back with the userland %gs. I implemented this by testing TF_CS to see if we're coming from supervisor mode already, and check for returning to supervisor. To avoid a race with interrupts in the brief period after beginning executing the handler and before the swapgs, convert all trap gates to interrupt gates, and reenable interrupts immediately after the swapgs. I am not happy with this. There are other possible ways to do this that should be investigated. (eg: storing the GS.base MSR value in the trapframe) Add some sysarch functions to let the userland code get to this. Approved by: re (blanket amd64/*)
149 lines
4.9 KiB
ArmAsm
149 lines
4.9 KiB
ArmAsm
/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $FreeBSD$
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*/
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#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
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#define IRQ_BYTE(irq_num) ((irq_num) >> 3)
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#define ENABLE_ICU1 \
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movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
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outb %al,$IO_ICU1 /* ... to clear in service bit */
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#define ENABLE_ICU1_AND_2 \
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movb $ICU_EOI,%al ; /* as above */ \
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outb %al,$IO_ICU2 ; /* but do second icu first ... */ \
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outb %al,$IO_ICU1 /* ... then first icu */
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/*
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* Macros for interrupt interrupt entry, call to handler, and exit.
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*/
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#define FAST_INTR(irq_num, vec_name, enable_icus) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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subq $TF_RIP,%rsp ; /* skip dummy tf_err and tf_trapno */ \
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testb $SEL_RPL_MASK,TF_CS(%rsp) ; /* come from kernel? */ \
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jz 1f ; /* Yes, dont swapgs again */ \
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swapgs ; \
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1: movq %rdi,TF_RDI(%rsp) ; \
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movq %rsi,TF_RSI(%rsp) ; \
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movq %rdx,TF_RDX(%rsp) ; \
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movq %rcx,TF_RCX(%rsp) ; \
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movq %r8,TF_R8(%rsp) ; \
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movq %r9,TF_R9(%rsp) ; \
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movq %rax,TF_RAX(%rsp) ; \
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movq %rbx,TF_RBX(%rsp) ; \
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movq %rbp,TF_RBP(%rsp) ; \
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movq %r10,TF_R10(%rsp) ; \
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movq %r11,TF_R11(%rsp) ; \
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movq %r12,TF_R12(%rsp) ; \
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movq %r13,TF_R13(%rsp) ; \
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movq %r14,TF_R14(%rsp) ; \
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movq %r15,TF_R15(%rsp) ; \
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FAKE_MCOUNT((12)*4(%rsp)) ; \
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call critical_enter ; \
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movq PCPU(CURTHREAD),%rbx ; \
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incl TD_INTR_NESTING_LEVEL(%rbx) ; \
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movq intr_unit + (irq_num) * 8, %rdi ; \
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call *intr_handler + (irq_num) * 8 ; /* do the work ASAP */ \
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enable_icus ; /* (re)enable ASAP (helps edge trigger?) */ \
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incl cnt+V_INTR ; /* book-keeping can wait */ \
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movq intr_countp + (irq_num) * 8,%rax ; \
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incq (%rax) ; \
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decl TD_INTR_NESTING_LEVEL(%rbx) ; \
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call critical_exit ; \
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MEXITCOUNT ; \
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jmp doreti
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/*
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* Slow, threaded interrupts.
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*
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* XXX Most of the parameters here are obsolete. Fix this when we're
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* done.
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* XXX we really shouldn't return via doreti if we just schedule the
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* interrupt handler and don't run anything. We could just do an
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* iret. FIXME.
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*/
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#define INTR(irq_num, vec_name, icu, enable_icus, maybe_extra_ipending) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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subq $TF_RIP,%rsp ; /* skip dummy tf_err and tf_trapno */ \
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testb $SEL_RPL_MASK,TF_CS(%rsp) ; /* come from kernel? */ \
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jz 1f ; /* Yes, dont swapgs again */ \
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swapgs ; \
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1: movq %rdi,TF_RDI(%rsp) ; \
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movq %rsi,TF_RSI(%rsp) ; \
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movq %rdx,TF_RDX(%rsp) ; \
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movq %rcx,TF_RCX(%rsp) ; \
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movq %r8,TF_R8(%rsp) ; \
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movq %r9,TF_R9(%rsp) ; \
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movq %rax,TF_RAX(%rsp) ; \
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movq %rbx,TF_RBX(%rsp) ; \
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movq %rbp,TF_RBP(%rsp) ; \
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movq %r10,TF_R10(%rsp) ; \
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movq %r11,TF_R11(%rsp) ; \
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movq %r12,TF_R12(%rsp) ; \
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movq %r13,TF_R13(%rsp) ; \
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movq %r14,TF_R14(%rsp) ; \
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movq %r15,TF_R15(%rsp) ; \
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maybe_extra_ipending ; \
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movb imen + IRQ_BYTE(irq_num),%al ; \
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orb $IRQ_BIT(irq_num),%al ; \
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movb %al,imen + IRQ_BYTE(irq_num) ; \
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outb %al,$icu+ICU_IMR_OFFSET ; \
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enable_icus ; \
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movq PCPU(CURTHREAD),%rbx ; \
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incl TD_INTR_NESTING_LEVEL(%rbx) ; \
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FAKE_MCOUNT(13*4(%rsp)) ; /* XXX late to avoid double count */ \
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movq $irq_num, %rdi; /* pass the IRQ */ \
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call sched_ithd ; \
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decl TD_INTR_NESTING_LEVEL(%rbx) ; \
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MEXITCOUNT ; \
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/* We could usually avoid the following jmp by inlining some of */ \
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/* doreti, but it's probably better to use less cache. */ \
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jmp doreti
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MCOUNT_LABEL(bintr)
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FAST_INTR(0,fastintr0, ENABLE_ICU1)
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FAST_INTR(1,fastintr1, ENABLE_ICU1)
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FAST_INTR(2,fastintr2, ENABLE_ICU1)
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FAST_INTR(3,fastintr3, ENABLE_ICU1)
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FAST_INTR(4,fastintr4, ENABLE_ICU1)
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FAST_INTR(5,fastintr5, ENABLE_ICU1)
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FAST_INTR(6,fastintr6, ENABLE_ICU1)
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FAST_INTR(7,fastintr7, ENABLE_ICU1)
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FAST_INTR(8,fastintr8, ENABLE_ICU1_AND_2)
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FAST_INTR(9,fastintr9, ENABLE_ICU1_AND_2)
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FAST_INTR(10,fastintr10, ENABLE_ICU1_AND_2)
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FAST_INTR(11,fastintr11, ENABLE_ICU1_AND_2)
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FAST_INTR(12,fastintr12, ENABLE_ICU1_AND_2)
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FAST_INTR(13,fastintr13, ENABLE_ICU1_AND_2)
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FAST_INTR(14,fastintr14, ENABLE_ICU1_AND_2)
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FAST_INTR(15,fastintr15, ENABLE_ICU1_AND_2)
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#define CLKINTR_PENDING movl $1,CNAME(clkintr_pending)
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/* Threaded interrupts */
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INTR(0,intr0, IO_ICU1, ENABLE_ICU1, CLKINTR_PENDING)
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INTR(1,intr1, IO_ICU1, ENABLE_ICU1,)
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INTR(2,intr2, IO_ICU1, ENABLE_ICU1,)
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INTR(3,intr3, IO_ICU1, ENABLE_ICU1,)
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INTR(4,intr4, IO_ICU1, ENABLE_ICU1,)
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INTR(5,intr5, IO_ICU1, ENABLE_ICU1,)
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INTR(6,intr6, IO_ICU1, ENABLE_ICU1,)
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INTR(7,intr7, IO_ICU1, ENABLE_ICU1,)
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INTR(8,intr8, IO_ICU2, ENABLE_ICU1_AND_2,)
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INTR(9,intr9, IO_ICU2, ENABLE_ICU1_AND_2,)
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INTR(10,intr10, IO_ICU2, ENABLE_ICU1_AND_2,)
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INTR(11,intr11, IO_ICU2, ENABLE_ICU1_AND_2,)
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INTR(12,intr12, IO_ICU2, ENABLE_ICU1_AND_2,)
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INTR(13,intr13, IO_ICU2, ENABLE_ICU1_AND_2,)
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INTR(14,intr14, IO_ICU2, ENABLE_ICU1_AND_2,)
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INTR(15,intr15, IO_ICU2, ENABLE_ICU1_AND_2,)
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MCOUNT_LABEL(eintr)
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