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49396cced3
through fork_trampoline. This was caused because we were clearing the SR_INT_IE and setting SR_EXL bits of the status register at the same time. This meant that if an interrupt happened while this MTC0 was making its way through the pipeline the exception processing would see the status register with SR_EXL bit set. This in turn would mean that the COP_0_EXC_PC would not be updated so the return from exception would be to an incorrect address. It is easy to verify this fix by a program that forks in a loop and the child just exits: while (1) { pid_t pid = vfork(); if (pid == 0) _exit(0); if (pid != -1) waitpid(pid, NULL, 0); } Also remove two instances where we set SR_EXL bit gratuitously in exception.S. Approved by: imp (mentor) |
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.. | ||
_align.h | ||
_bus_octeon.h | ||
_bus.h | ||
_inttypes.h | ||
_limits.h | ||
_stdint.h | ||
_types.h | ||
archtype.h | ||
asm.h | ||
asmacros.h | ||
atomic.h | ||
bootinfo.h | ||
bswap.h | ||
bus_dma.h | ||
bus.h | ||
cache_mipsNN.h | ||
cache_r4k.h | ||
cache.h | ||
cdefs.h | ||
clock.h | ||
clockvar.h | ||
cpu.h | ||
cpufunc.h | ||
cpuinfo.h | ||
cpuregs.h | ||
cputypes.h | ||
db_machdep.h | ||
defs.h | ||
elf.h | ||
endian.h | ||
exec.h | ||
float.h | ||
floatingpoint.h | ||
fls64.h | ||
fpu.h | ||
frame.h | ||
gdb_machdep.h | ||
hwfunc.h | ||
ieee.h | ||
ieeefp.h | ||
in_cksum.h | ||
intr_machdep.h | ||
iodev.h | ||
kdb.h | ||
limits.h | ||
locore.h | ||
md_var.h | ||
memdev.h | ||
metadata.h | ||
minidump.h | ||
mips_opcode.h | ||
mp_watchdog.h | ||
mutex.h | ||
param.h | ||
pcb.h | ||
pci_cfgreg.h | ||
pcpu.h | ||
pmap.h | ||
pmc_mdep.h | ||
ppireg.h | ||
proc.h | ||
profile.h | ||
psl.h | ||
pte.h | ||
ptrace.h | ||
queue.h | ||
reg.h | ||
regdef.h | ||
regnum.h | ||
reloc.h | ||
resource.h | ||
rm7000.h | ||
runq.h | ||
segments.h | ||
setjmp.h | ||
sf_buf.h | ||
sigframe.h | ||
signal.h | ||
smp.h | ||
stdarg.h | ||
sysarch.h | ||
timerreg.h | ||
trap.h | ||
ucontext.h | ||
varargs.h | ||
vm.h | ||
vmparam.h |