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124 lines
5.1 KiB
C
124 lines
5.1 KiB
C
/*
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* Copyright (c) 1995 John Hay.
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* Copyright (c) 1996 SDL Communications, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _IF_SRREGS_H_
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#define _IF_SRREGS_H_
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#define NCHAN 2 /* A HD64570 chip have 2 channels */
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#define SR_BUF_SIZ 512
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#define SR_TX_BLOCKS 2 /* Sepperate sets of tx buffers */
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#define SR_CRD_N2 1
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#define SR_CRD_N2PCI 2
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/*
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* RISCom/N2 ISA card.
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*/
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#define SRC_IO_SIZ 0x10 /* Actually a lie. It uses a lot more. */
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#define SRC_WIN_SIZ 0x00004000
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#define SRC_WIN_MSK (SRC_WIN_SIZ - 1)
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#define SRC_WIN_SHFT 14
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#define SR_FLAGS_NCHAN_MSK 0x0000000F
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#define SR_FLAGS_0_CLK_MSK 0x00000030
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#define SR_FLAGS_0_EXT_CLK 0x00000000 /* External RX clock shared by TX */
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#define SR_FLAGS_0_EXT_SEP_CLK 0x00000010 /* Sepperate external clocks */
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#define SR_FLAGS_0_INT_CLK 0x00000020 /* Internal clock */
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#define SR_FLAGS_1_CLK_MSK 0x000000C0
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#define SR_FLAGS_1_EXT_CLK 0x00000000 /* External RX clock shared by TX */
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#define SR_FLAGS_1_EXT_SEP_CLK 0x00000040 /* Sepperate external clocks */
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#define SR_FLAGS_1_INT_CLK 0x00000080 /* Internal clock */
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#define SR_FLAGS_CLK_SHFT 4
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#define SR_FLAGS_CLK_CHAN_SHFT 2
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#define SR_FLAGS_EXT_CLK 0x00000000 /* External RX clock shared by TX */
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#define SR_FLAGS_EXT_SEP_CLK 0x00000001 /* Sepperate external clocks */
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#define SR_FLAGS_INT_CLK 0x00000002 /* Internal clock */
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#define SR_PCR 0x00 /* RW, PC Control Register */
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#define SR_BAR 0x02 /* RW, Base Address Register */
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#define SR_PSR 0x04 /* RW, Page Scan Register */
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#define SR_MCR 0x06 /* RW, Modem Control Register */
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#define SR_PCR_SCARUN 0x01 /* !Reset */
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#define SR_PCR_EN_VPM 0x02 /* Running above 1M */
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#define SR_PCR_MEM_WIN 0x04 /* Open memory window */
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#define SR_PCR_ISA16 0x08 /* 16 bit ISA mode */
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#define SR_PCR_16M_SEL 0xF0 /* A20-A23 Addresses */
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#define SR_PSR_PG_SEL 0x1F /* Page 0 - 31 select */
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#define SR_PG_MSK 0x1F
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#define SR_PSR_WIN_SIZ 0x60 /* Window size select */
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#define SR_PSR_WIN_16K 0x00
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#define SR_PSR_WIN_32K 0x20
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#define SR_PSR_WIN_64K 0x40
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#define SR_PSR_WIN_128K 0x60
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#define SR_PSR_EN_SCA_DMA 0x80 /* Enable the SCA DMA */
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#define SR_MCR_DTR0 0x01 /* Deactivate DTR0 */
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#define SR_MCR_DTR1 0x02 /* Deactivate DTR1 */
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#define SR_MCR_DSR0 0x04 /* DSR0 Status */
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#define SR_MCR_DSR1 0x08 /* DSR1 Status */
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#define SR_MCR_TE0 0x10 /* Enable RS422 TXD */
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#define SR_MCR_TE1 0x20 /* Enable RS422 TXD */
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#define SR_MCR_ETC0 0x40 /* Enable Ext Clock out */
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#define SR_MCR_ETC1 0x80 /* Enable Ext Clock out */
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/*
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* RISCom/N2 PCI card.
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*/
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#define SR_FECR 0x0200 /* Front End Control Register */
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#define SR_FECR_ETC0 0x0001 /* Enable Ext Clock out */
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#define SR_FECR_ETC1 0x0002 /* Enable Ext Clock out */
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#define SR_FECR_TE0 0x0004 /* Enable RS422 TXD */
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#define SR_FECR_TE1 0x0008 /* Enable RS422 TXD */
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#define SR_FECR_GPO0 0x0010 /* General Purpose Output */
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#define SR_FECR_GPO1 0x0020 /* General Purpose Output */
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#define SR_FECR_DTR0 0x0040 /* 0 for active, 1 for inactive */
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#define SR_FECR_DTR1 0x0080 /* 0 for active, 1 for inactive */
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#define SR_FECR_DSR0 0x0100 /* DSR0 Status */
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#define SR_FECR_ID0 0x0E00 /* ID of channel 0 */
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#define SR_FECR_DSR1 0x1000 /* DSR1 Status */
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#define SR_FECR_ID1 0xE000 /* ID of channel 1 */
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#define SR_FE_ID_V35 0x00 /* V.35 Interface */
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#define SR_FE_ID_RS232 0x01 /* RS232 Interface */
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#define SR_FE_ID_TEST 0x02 /* Test Board */
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#define SR_FE_ID_RS422 0x03 /* RS422 Interface */
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#define SR_FE_ID_HSSI 0x05 /* HSSI Interface */
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#define SR_FE_ID_X21 0x06 /* X.21 Interface */
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#define SR_FE_ID_NONE 0x07 /* No card present */
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#define SR_FE_ID0_SHFT 9
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#define SR_FE_ID1_SHFT 13
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#endif /* _IF_SRREGS_H_ */
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