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b39b673d37
Keep track of interrupt nesting level. It is normally 0 for syscalls and traps, but is fudged to 1 for their exit processing in case they metamorphose into an interrupt handler. i386/genassym.c; Remove support for the obsolete pcb_iml and pcb_cmap2. Add support for pcb_inl. i386/swtch.s: Fudge the interrupt nesting level across context switches and in the idle loop so that the work for preemptive context switches gets counted as interrupt time, the work for voluntary context switches gets counted mostly as system time (the part when curproc == 0 gets counted as interrupt time), and only truly idle time gets counted as idle time. Remove obsolete support (commented out and otherwise) for pcb_iml. Load curpcb just before curproc instead of just after so that curpcb is always valid if curproc is. A few more changes like this may fix tracing through context switches. Remove obsolete function swtch_to_inactive(). include/cpu.h: Use the new interrupt nesting level variable to implement a non-fake CLF_INTR() so that accounting for the interrupt state works. You can use top, iostat or (best) an up to date systat to see interrupt overheads. I see the expected huge interrupt overheads for ISA devices (on a 486DX/33, about 55% for an IDE drive transferring 1250K/sec and the same for a WD8013EBT network card transferring 1100K/sec). The huge interrupt overheads for serial devices are unfortunately normally invisible. include/pcb.h: Remove the obsolete pcb_iml and pcb_cmap2. Replace them by padding to preserve binary compatibility. Use part of the new padding for pcb_inl. isa/icu.s: isa/vector.s: Keep track of interrupt nesting level.
297 lines
9.2 KiB
ArmAsm
297 lines
9.2 KiB
ArmAsm
/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $Id: vector.s,v 1.10 1994/11/01 23:29:50 bde Exp $
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*/
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#include <i386/isa/icu.h>
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#include <i386/isa/isa.h>
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#define ICU_EOI 0x20 /* XXX - define elsewhere */
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#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
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#define IRQ_BYTE(irq_num) ((irq_num) / 8)
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#ifdef AUTO_EOI_1
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#define ENABLE_ICU1 /* use auto-EOI to reduce i/o */
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#else
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#define ENABLE_ICU1 \
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movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
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FASTER_NOP ; /* ... ASAP ... */ \
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outb %al,$IO_ICU1 /* ... to clear in service bit */
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#endif
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#ifdef AUTO_EOI_2
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/*
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* The data sheet says no auto-EOI on slave, but it sometimes works.
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*/
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#define ENABLE_ICU1_AND_2 ENABLE_ICU1
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#else
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#define ENABLE_ICU1_AND_2 \
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movb $ICU_EOI,%al ; /* as above */ \
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FASTER_NOP ; \
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outb %al,$IO_ICU2 ; /* but do second icu first */ \
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FASTER_NOP ; \
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outb %al,$IO_ICU1 /* then first icu */
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#endif
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#ifdef FAST_INTR_HANDLER_USES_ES
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#define ACTUALLY_PUSHED 1
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#define MAYBE_MOVW_AX_ES movl %ax,%es
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#define MAYBE_POPL_ES popl %es
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#define MAYBE_PUSHL_ES pushl %es
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#else
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/*
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* We can usually skip loading %es for fastintr handlers. %es should
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* only be used for string instructions, and fastintr handlers shouldn't
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* do anything slow enough to justify using a string instruction.
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*/
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#define ACTUALLY_PUSHED 0
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#define MAYBE_MOVW_AX_ES
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#define MAYBE_POPL_ES
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#define MAYBE_PUSHL_ES
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#endif
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/*
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* Macros for interrupt interrupt entry, call to handler, and exit.
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*
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* XXX - the interrupt frame is set up to look like a trap frame. This is
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* usually a waste of time. The only interrupt handlers that want a frame
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* are the clock handler (it wants a clock frame), the npx handler (it's
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* easier to do right all in assembler). The interrupt return routine
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* needs a trap frame for rare AST's (it could easily convert the frame).
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* The direct costs of setting up a trap frame are two pushl's (error
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* code and trap number), an addl to get rid of these, and pushing and
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* popping the call-saved regs %esi, %edi and %ebp twice, The indirect
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* costs are making the driver interface nonuniform so unpending of
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* interrupts is more complicated and slower (call_driver(unit) would
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* be easier than ensuring an interrupt frame for all handlers. Finally,
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* there are some struct copies in the npx handler and maybe in the clock
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* handler that could be avoided by working more with pointers to frames
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* instead of frames.
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*
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* XXX - should we do a cld on every system entry to avoid the requirement
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* for scattered cld's?
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*
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* Coding notes for *.s:
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*
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* If possible, avoid operations that involve an operand size override.
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* Word-sized operations might be smaller, but the operand size override
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* makes them slower on on 486's and no faster on 386's unless perhaps
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* the instruction pipeline is depleted. E.g.,
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*
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* Use movl to seg regs instead of the equivalent but more descriptive
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* movw - gas generates an irelevant (slower) operand size override.
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*
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* Use movl to ordinary regs in preference to movw and especially
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* in preference to movz[bw]l. Use unsigned (long) variables with the
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* top bits clear instead of unsigned short variables to provide more
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* opportunities for movl.
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*
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* If possible, use byte-sized operations. They are smaller and no slower.
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*
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* Use (%reg) instead of 0(%reg) - gas generates larger code for the latter.
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*
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* If the interrupt frame is made more flexible, INTR can push %eax first
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* and decide the ipending case with less overhead, e.g., by avoiding
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* loading segregs.
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*/
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#define FAST_INTR(irq_num, enable_icus) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(fastintr/**/irq_num) ; \
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pushl %eax ; /* save only call-used registers */ \
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pushl %ecx ; \
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pushl %edx ; \
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pushl %ds ; \
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MAYBE_PUSHL_ES ; \
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movl $KDSEL,%eax ; \
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movl %ax,%ds ; \
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MAYBE_MOVW_AX_ES ; \
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FAKE_MCOUNT((4+ACTUALLY_PUSHED)*4(%esp)) ; \
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pushl _intr_unit + (irq_num) * 4 ; \
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call *_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
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enable_icus ; /* (re)enable ASAP (helps edge trigger?) */ \
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addl $4,%esp ; \
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incl _cnt+V_INTR ; /* book-keeping can wait */ \
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movl _intr_countp + (irq_num) * 4,%eax ; \
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incl (%eax) ; \
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movl _cpl,%eax ; /* are we unmasking pending HWIs or SWIs? */ \
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notl %eax ; \
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andl _ipending,%eax ; \
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jne 1f ; /* yes, handle them */ \
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MEXITCOUNT ; \
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MAYBE_POPL_ES ; \
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popl %ds ; \
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popl %edx ; \
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popl %ecx ; \
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popl %eax ; \
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iret ; \
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; \
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ALIGN_TEXT ; \
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1: ; \
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movl _cpl,%eax ; \
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movl $HWI_MASK|SWI_MASK,_cpl ; /* limit nesting ... */ \
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sti ; /* ... to do this as early as possible */ \
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MAYBE_POPL_ES ; /* discard most of thin frame ... */ \
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popl %ecx ; /* ... original %ds ... */ \
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popl %edx ; \
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xchgl %eax,(1+ACTUALLY_PUSHED)*4(%esp) ; /* orig %eax; save cpl */ \
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pushal ; /* build fat frame (grrr) ... */ \
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pushl %ecx ; /* ... actually %ds ... */ \
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pushl %es ; \
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movl $KDSEL,%eax ; \
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movl %ax,%es ; \
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movl (2+8+0)*4(%esp),%ecx ; /* ... %ecx from thin frame ... */ \
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movl %ecx,(2+6)*4(%esp) ; /* ... to fat frame ... */ \
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movl (2+8+1)*4(%esp),%eax ; /* ... cpl from thin frame */ \
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pushl %eax ; \
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subl $4,%esp ; /* junk for unit number */ \
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incb _intr_nesting_level ; \
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MEXITCOUNT ; \
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jmp _doreti
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#define INTR(irq_num, icu, enable_icus, reg) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(intr/**/irq_num) ; \
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pushl $0 ; /* dumby error code */ \
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pushl $0 ; /* dumby trap type */ \
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pushal ; \
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pushl %ds ; /* save our data and extra segments ... */ \
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pushl %es ; \
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movl $KDSEL,%eax ; /* ... and reload with kernel's own ... */ \
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movl %ax,%ds ; /* ... early for obsolete reasons */ \
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movl %ax,%es ; \
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movb _imen + IRQ_BYTE(irq_num),%al ; \
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orb $IRQ_BIT(irq_num),%al ; \
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movb %al,_imen + IRQ_BYTE(irq_num) ; \
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FASTER_NOP ; \
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outb %al,$icu+1 ; \
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enable_icus ; \
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incl _cnt+V_INTR ; /* tally interrupts */ \
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movl _cpl,%eax ; \
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testb $IRQ_BIT(irq_num),%reg ; \
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jne 2f ; \
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incb _intr_nesting_level ; \
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Xresume/**/irq_num: ; \
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FAKE_MCOUNT(12*4(%esp)) ; /* XXX late to avoid double count */ \
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movl _intr_countp + (irq_num) * 4,%eax ; \
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incl (%eax) ; \
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movl _cpl,%eax ; \
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pushl %eax ; \
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pushl _intr_unit + (irq_num) * 4 ; \
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orl _intr_mask + (irq_num) * 4,%eax ; \
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movl %eax,_cpl ; \
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sti ; \
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call *_intr_handler + (irq_num) * 4 ; \
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cli ; /* must unmask _imen and icu atomically */ \
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movb _imen + IRQ_BYTE(irq_num),%al ; \
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andb $~IRQ_BIT(irq_num),%al ; \
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movb %al,_imen + IRQ_BYTE(irq_num) ; \
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FASTER_NOP ; \
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outb %al,$icu+1 ; \
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sti ; /* XXX _doreti repeats the cli/sti */ \
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MEXITCOUNT ; \
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/* We could usually avoid the following jmp by inlining some of */ \
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/* _doreti, but it's probably better to use less cache. */ \
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jmp _doreti ; \
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; \
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ALIGN_TEXT ; \
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2: ; \
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/* XXX skip mcounting here to avoid double count */ \
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orb $IRQ_BIT(irq_num),_ipending + IRQ_BYTE(irq_num) ; \
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popl %es ; \
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popl %ds ; \
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popal ; \
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addl $4+4,%esp ; \
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iret
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MCOUNT_LABEL(bintr)
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FAST_INTR(0, ENABLE_ICU1)
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FAST_INTR(1, ENABLE_ICU1)
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FAST_INTR(2, ENABLE_ICU1)
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FAST_INTR(3, ENABLE_ICU1)
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FAST_INTR(4, ENABLE_ICU1)
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FAST_INTR(5, ENABLE_ICU1)
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FAST_INTR(6, ENABLE_ICU1)
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FAST_INTR(7, ENABLE_ICU1)
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FAST_INTR(8, ENABLE_ICU1_AND_2)
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FAST_INTR(9, ENABLE_ICU1_AND_2)
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FAST_INTR(10, ENABLE_ICU1_AND_2)
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FAST_INTR(11, ENABLE_ICU1_AND_2)
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FAST_INTR(12, ENABLE_ICU1_AND_2)
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FAST_INTR(13, ENABLE_ICU1_AND_2)
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FAST_INTR(14, ENABLE_ICU1_AND_2)
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FAST_INTR(15, ENABLE_ICU1_AND_2)
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INTR(0, IO_ICU1, ENABLE_ICU1, al)
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INTR(1, IO_ICU1, ENABLE_ICU1, al)
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INTR(2, IO_ICU1, ENABLE_ICU1, al)
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INTR(3, IO_ICU1, ENABLE_ICU1, al)
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INTR(4, IO_ICU1, ENABLE_ICU1, al)
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INTR(5, IO_ICU1, ENABLE_ICU1, al)
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INTR(6, IO_ICU1, ENABLE_ICU1, al)
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INTR(7, IO_ICU1, ENABLE_ICU1, al)
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INTR(8, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(9, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(10, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(11, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(12, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(13, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(14, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(15, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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MCOUNT_LABEL(eintr)
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.data
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ihandlers: /* addresses of interrupt handlers */
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/* actually resumption addresses for HWI's */
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.long Xresume0, Xresume1, Xresume2, Xresume3
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.long Xresume4, Xresume5, Xresume6, Xresume7
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.long Xresume8, Xresume9, Xresume10, Xresume11
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.long Xresume12, Xresume13, Xresume14, Xresume15
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.long swi_tty, swi_net, 0, 0, 0, 0, 0, 0
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.long 0, 0, 0, 0, 0, 0, _softclock, swi_ast
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imasks: /* masks for interrupt handlers */
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.space NHWI*4 /* padding; HWI masks are elsewhere */
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.long SWI_TTY_MASK, SWI_NET_MASK, 0, 0, 0, 0, 0, 0
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.long 0, 0, 0, 0, 0, 0, SWI_CLOCK_MASK, SWI_AST_MASK
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.globl _intr_nesting_level
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_intr_nesting_level:
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.byte 0
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.space 3
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/*
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* Interrupt counters and names. The format of these and the label names
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* must agree with what vmstat expects. The tables are indexed by device
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* ids so that we don't have to move the names around as devices are
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* attached.
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*/
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#include "vector.h"
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.globl _intrcnt, _eintrcnt
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_intrcnt:
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.space (NR_DEVICES + ICU_LEN) * 4
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_eintrcnt:
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.globl _intrnames, _eintrnames
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_intrnames:
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.ascii DEVICE_NAMES
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.asciz "stray irq0"
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.asciz "stray irq1"
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.asciz "stray irq2"
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.asciz "stray irq3"
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.asciz "stray irq4"
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.asciz "stray irq5"
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.asciz "stray irq6"
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.asciz "stray irq7"
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.asciz "stray irq8"
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.asciz "stray irq9"
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.asciz "stray irq10"
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.asciz "stray irq11"
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.asciz "stray irq12"
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.asciz "stray irq13"
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.asciz "stray irq14"
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.asciz "stray irq15"
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_eintrnames:
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.text
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