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windows. Right now we only support pci chips that are memory mapped. These are the most common bridges in use today and will help a large majority of the users. I/O mapped PCI chips support this functionality in a different way, as do some of the ISA bridges (but only when mounted on a motherboard). These chips are not supported by this change.
332 lines
13 KiB
C
332 lines
13 KiB
C
/*
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* i82365.h - Definitions for Intel 82365 PCIC
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* PCMCIA Card Interface Controller
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*
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* originally by Barry Jaspan; hacked over by Keith Moore
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* hacked to unrecognisability by Andrew McRae (andrew@mega.com.au)
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*
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* Updated 3/3/95 to include Cirrus Logic stuff.
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*-------------------------------------------------------------------------
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*
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* Copyright (c) 2001 M. Warner Losh. All rights reserved.
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* Copyright (c) 1995 Andrew McRae. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define PCIC_I82365 0 /* Intel i82365SL-A/B or clone */
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#define PCIC_IBM 1 /* IBM clone */
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#define PCIC_VLSI 2 /* VLSI chip */
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#define PCIC_PD6722 3 /* Cirrus logic PD6722 */
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#define PCIC_PD6710 4 /* Cirrus logic PD6710 */
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#define PCIC_VG365 5 /* Vadem 365 */
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#define PCIC_VG465 6 /* Vadem 465 */
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#define PCIC_VG468 7 /* Vadem 468 */
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#define PCIC_VG469 8 /* Vadem 469 */
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#define PCIC_RF5C296 9 /* Ricoh RF5C296 */
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#define PCIC_RF5C396 10 /* Ricoh RF5C396 */
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#define PCIC_IBM_KING 11 /* IBM KING PCMCIA Controller */
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#define PCIC_I82365SL_DF 12 /* Intel i82365sl-DF step */
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#define PCIC_PD6729 13 /* Cirrus Logic PD6729 */
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#define PCIC_PD673X 14 /* Cirrus Logic PD673x */
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/*
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* Address of the controllers. Each controller can manage
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* two PCMCIA slots. Up to 8 slots are supported in total.
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* The PCIC controller is accessed via an index port and a
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* data port. The index port has the 8 bit address of the
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* register accessed via the data port. How I long for
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* real memory mapped I/O!
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* The top two bits of the index address are used to
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* identify the port number, and the lower 6 bits
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* select one of the 64 possible data registers.
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*/
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#define PCIC_INDEX 0 /* Index register */
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#define PCIC_DATA 1 /* Data register */
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#define PCIC_NPORT 2 /* Number of ports */
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#define PCIC_PORT_0 0x3e0 /* index reg, chips 0 and 1 */
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/*
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* Register index addresses.
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*/
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#define PCIC_ID_REV 0x00 /* Identification and Revision */
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#define PCIC_STATUS 0x01 /* Interface Status */
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#define PCIC_POWER 0x02 /* Power and RESETDRV control */
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#define PCIC_INT_GEN 0x03 /* Interrupt and General Control */
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#define PCIC_STAT_CHG 0x04 /* Card Status Change */
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#define PCIC_STAT_INT 0x05 /* Card Status Change Interrupt Config */
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#define PCIC_ADDRWINE 0x06 /* Address Window Enable */
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#define PCIC_IOCTL 0x07 /* I/O Control */
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#define PCIC_IO0 0x08 /* I/O Address 0 */
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#define PCIC_IO1 0x0c /* I/O Address 1 */
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#define PCIC_MEMBASE 0x10 /* Base of memory window registers */
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#define PCIC_CDGC 0x16 /* Card Detect and General Control */
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#define PCIC_MISC1 0x16 /* PD67xx: Misc control register 1 per slot */
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#define PCIC_GLO_CTRL 0x1e /* Global Control Register */
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#define PCIC_MISC2 0x1e /* PD67xx: Misc control register 2 per chip */
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#define PCIC_CLCHIP 0x1f /* PD67xx: Chip I/D */
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#define PCIC_EXT_IND 0x2e /* PD67xx: Extended Index */
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#define PCIC_EXTENDED 0x2f /* PD67xx: Extended register */
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#define PCIC_CVSR 0x2f /* Vadem: Voltage select register */
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#define PCIC_RICOH_MCR2 0x2f /* Ricoh: Mode Control Register 2 */
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#define PCIC_VMISC 0x3a /* Vadem: Misc control register */
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#define PCIC_RICOH_ID 0x3a /* Ricoh: ID register */
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#define PCIC_TOPIC_FCR 0x3e /* Toshiba ToPIC: Function Control Register */
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#define PCIC_TIME_SETUP0 0x3a
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#define PCIC_TIME_CMD0 0x3b
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#define PCIC_TIME_RECOV0 0x3c
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#define PCIC_TIME_SETUP1 0x3d
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#define PCIC_TIME_CMD1 0x3e
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#define PCIC_TIME_RECOV1 0x3f
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/* Yenta only registers */
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#define PCIC_MEMORY_HIGH0 0x40 /* A31..A25 of mapping addres for */
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#define PCIC_MEMORY_HIGH1 0x41 /* the memory windows. */
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#define PCIC_MEMORY_HIGH2 0x42
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#define PCIC_MEMORY_HIGH3 0x43
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#define PCIC_SLOT_SIZE 0x40 /* Size of register set for one slot */
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/* Now register bits, ordered by reg # */
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/* For Identification and Revision (PCIC_ID_REV) */
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#define PCIC_INTEL0 0x82 /* Intel 82365SL Rev. 0; Both Memory and I/O */
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#define PCIC_INTEL1 0x83 /* Intel 82365SL Rev. 1; Both Memory and I/O */
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#define PCIC_INTEL2 0x84 /* Intel 82365SL step D */
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#define PCIC_VLSI82C146 0x84 /* VLSI 82C146 */
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#define PCIC_IBM1 0x88 /* IBM PCIC clone; Both Memory and I/O */
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#define PCIC_IBM2 0x89 /* IBM PCIC clone; Both Memory and I/O */
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#define PCIC_IBM3 0x8a /* IBM KING PCIC clone; Both Memory and I/O */
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/* For Interface Status register (PCIC_STATUS) */
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#define PCIC_VPPV 0x80 /* Vpp_valid or reserved*/
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#define PCIC_RICOH_5VCARD 0x80 /* 5V card detected */
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#define PCIC_POW 0x40 /* PC Card power active */
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#define PCIC_READY 0x20 /* Ready/~Busy */
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#define PCIC_MWP 0x10 /* Memory Write Protect */
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#define PCIC_CD 0x0C /* Both card detect bits */
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#define PCIC_BVD 0x03 /* Both Battery Voltage Detect bits */
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/* For the Power and RESETDRV register (PCIC_POWER) */
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#define PCIC_OUTENA 0x80 /* Output Enable */
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#define PCIC_DISRST 0x40 /* Disable RESETDRV */
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#define PCIC_APSENA 0x20 /* Auto Pwer Switch Enable */
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#define PCIC_PCPWRE 0x10 /* PC Card Power Enable */
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#define PCIC_VCC 0x18 /* Vcc control bits */
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#define PCIC_VCC_5V 0x10 /* 5 volts */
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#define PCIC_VCC_ON 0x10 /* Turn on VCC on some chips. */
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#define PCIC_VCC_3V 0x18 /* 3 volts */
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#define PCIC_VCC_5V_KING 0x14 /* 5 volts for KING PCIC */
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#define PCIC_VPP 0x03 /* Vpp control bits */
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#define PCIC_VPP_5V 0x01 /* 5 volts */
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#define PCIC_VPP_12V 0x02 /* 12 volts */
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/* For the Interrupt and General Control register (PCIC_INT_GEN) */
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#define PCIC_CARDRESET 0x40 /* Card reset 0 = Reset, 1 = Normal */
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#define PCIC_CARDTYPE 0x20 /* Card Type 0 = memory, 1 = I/O */
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#define PCIC_IOCARD 0x20
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#define PCIC_MEMCARD 0x00
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#define PCIC_INTR_ENA 0x10 /* PCI CSC Interrupt enable */
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/* For the Card Status Change register (PCIC_STAT_CHG) */
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#define PCIC_CDTCH 0x08 /* Card Detect Change */
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#define PCIC_RDYCH 0x04 /* Ready Change */
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#define PCIC_BATWRN 0x02 /* Battery Warning */
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#define PCIC_BATDED 0x01 /* Battery Dead */
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/* For the Card status change interrupt PCIC_STAT_INT */
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#define PCIC_CSCSELECT 0xf0 /* CSCSELECT */
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#define PCIC_SI_IRQ_SHIFT 4
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#define PCIC_CDEN 0x8
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#define PCIC_READYEN 0x4
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#define PCIC_BATWARNEN 0x2
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#define PCIC_BATDEADEN 0x1
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/*
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* For the Address Window Enable Register (PCIC_ADDRWINE)
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* The lower 6 bits contain enable bits for the memory
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* windows (LSB = memory window 0).
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*/
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#define PCIC_MEMCS16 0x20 /* ~MEMCS16 Decode A23-A12 */
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#define PCIC_IO0_EN 0x40 /* I/O Window 0 Enable */
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#define PCIC_IO1_EN 0x80 /* I/O Window 1 Enable */
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/*
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* For the I/O Control Register (PCIC_IOCTL)
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* The lower nybble is the flags for I/O window 0
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* The upper nybble is the flags for I/O window 1
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*/
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#define PCIC_IO_16BIT 0x01 /* I/O to this segment is 16 bit */
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#define PCIC_IO_CS16 0x02 /* I/O cs16 source is the card */
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#define PCIC_IO_0WS 0x04 /* zero wait states added on 8 bit cycles */
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#define PCIC_IO_WS 0x08 /* Wait states added for 16 bit cycles */
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/*
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* The memory window registers contain the start and end
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* physical host address that the PCIC maps to the card,
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* and an offset calculated from the card memory address.
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* All values are shifted down 12 bits, so allocation is
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* done in 4Kb blocks. Only 12 bits of each value is
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* stored, limiting the range to the ISA address size of
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* 24 bits. The upper 4 bits of the most significant byte
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* within the values are used for various flags.
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*
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* The layout is:
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*
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* base+0 : lower 8 bits of system memory start address
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* base+1 : upper 4 bits of system memory start address + flags
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* base+2 : lower 8 bits of system memory end address
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* base+3 : upper 4 bits of system memory end address + flags
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* base+4 : lower 8 bits of offset to card address
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* base+5 : upper 4 bits of offset to card address + flags
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*
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* The following two bytes are reserved for other use.
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*/
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#define PCIC_MEMSIZE 8
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/*
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* Flags for system memory start address upper byte
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*/
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#define PCIC_ZEROWS 0x40 /* Zero wait states */
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#define PCIC_DATA16 0x80 /* Data width is 16 bits */
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/*
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* Flags for system memory end address upper byte
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*/
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#define PCIC_MW0 0x40 /* Wait state bit 0 */
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#define PCIC_MW1 0x80 /* Wait state bit 1 */
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/*
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* Flags for card offset upper byte
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*/
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#define PCIC_REG 0x40 /* Attribute/Common select (why called Reg?) */
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#define PCIC_WP 0x80 /* Write-protect this window */
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/* For Card Detect and General Control register (PCIC_CDGC) */
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#define PCIC_16_DL_INH 0x01 /* 16-bit memory delay inhibit */
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#define PCIC_CNFG_RST_EN 0x02 /* configuration reset enable */
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#define PCIC_GPI_EN 0x04 /* GPI Enable */
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#define PCIC_GPI_TRANS 0x08 /* GPI Transition Control */
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#define PCIC_CDRES_EN 0x10 /* card detect resume enable */
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#define PCIC_SW_CD_INT 0x20 /* s/w card detect interrupt */
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#define PCIC_VS1STAT 0x40 /* 0 VS1# low, 1 VS1# high */
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#define PCIC_VS2STAT 0x80 /* 0 VS2# low, 1 VS2# high */
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/* CL-PD67[12]x: For 3.3V cards, etc. (PCIC_MISC1) */
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#define PCIC_MISC1_5V_DETECT 0x01 /* PD6710 only */
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#define PCIC_MISC1_VCC_33 0x02 /* Set Vcc is 3.3V, else 5.0V */
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#define PCIC_MISC1_PMINT 0x04 /* Pulse management intr */
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#define PCIC_MISC1_PCINT 0x08 /* Pulse card interrupt */
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#define PCIC_MISC1_SPEAKER 0x10 /* Enable speaker */
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#define PCIC_MISC1_INPACK 0x80 /* INPACK throttles data */
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/* i82365B and newer (!PD67xx) Global Control register (PCIC_GLO_CTRL) */
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#define PCIC_PWR_DOWN 0x01 /* power down */
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#define PCIC_LVL_MODE 0x02 /* level mode interrupt enable */
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#define PCIC_WB_CSCINT 0x04 /* explicit write-back csc intr */
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/* Rev B only */
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#define PCIC_IRQ0_LEVEL 0x08 /* irq 14 pulse mode enable */
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#define PCIC_IRQ1_LEVEL 0x10
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/* CL-PD67[12]x: For Misc. Control Register 2 (PCIC_MISC2) */
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#define PCIC_LPDM_EN 0x02 /* Cirrus PD672x: low power dynamic mode */
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/* CL-PD67[12]x: Chip info (PCIC_CLCHIP) */
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#define PCIC_CLC_TOGGLE 0xc0 /* These bits toggle 1 -> 0 */
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#define PCIC_CLC_DUAL 0x20 /* Single/dual socket version */
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/* Cirrus Logic: Extended Registers (PCIC_EXT_IND) */
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#define PCIC_EXT_DATA 0x0a /* External Data */
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/* EXT_DATA */
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#define PCIC_VS1A 0x01
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#define PCIC_VS2A 0x02
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#define PCIC_VS1B 0x04
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#define PCIC_VS2B 0x08
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/* Cirrus Logic: Extended register Extension Control 1 */
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#define PCIC_EXTCTRL1 0x03
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#define PCIC_EC1_VCC_LOCK 0x1 /* Vcc Power locked to s/w change */
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#define PCIC_EC1_AUTO_POWER_CLEAR 0x2 /* Vcc power cleared on eject? */
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#define PCIC_EC1_LED_ENABLE 0x4 /* LED activity enable */
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#define PCIC_EC1_CARD_IRQ_INV 0x8 /* Card IRQ level inverted for pci? */
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#define PCIC_EC1_CSC_IRQ_INV 0x10 /* CSC IRQ level inverted for pci? */
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#define PCIC_EC1_PULLUP 0x20 /* Dis pullup when 1. */
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/* Vadem: Card Voltage Select register (PCIC_CVSR) */
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#define PCIC_CVSR_VS 0x03 /* Voltage select */
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#define PCIC_CVSR_VS_5 0x00 /* 5.0 V */
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#define PCIC_CVSR_VS_33a 0x01 /* alt 3.3V */
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#define PCIC_CVSR_VS_XX 0x02 /* X.XV when available */
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#define PCIC_CVSR_VS_33 0x03 /* 3.3V */
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/* Ricoh: Misc Control Register 2 (PCIC_RICOH_MCR2) */
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#define PCIC_MCR2_VCC_33 0x01 /* 3.3V */
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/* Vadem: misc register (PCIC_VMISC) */
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#define PCIC_VADEMREV 0x40
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/* Ricoh: ID register values (PCIC_RICOH_ID) */
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#define PCIC_RID_296 0x32
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#define PCIC_RID_396 0xb2
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/* Toshiba ToPIC: Function Control Register */
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#define PCIC_FCR_3V_EN 0x01 /* Enable 3V cards */
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#define PCIC_FCR_VS_EN 0x02 /* Voltage Sense enable */
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/*
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* Mask of allowable interrupts.
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*
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* For IBM-AT machines, irqs 3, 4, 5, 7, 9, 10, 11, 12, 14, 15 are
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* allowed. Nearly all IBM-AT machines with pcic cards or bridges
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* wire these interrupts (or a subset thereof) to the corresponding
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* pins on the ISA bus. Some older laptops are reported to not route
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* all the interrupt pins to the bus because the designers knew that
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* some would conflict with builtin devices.
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*
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* For NEC PC98 machines, irq 3, 5, 6, 9, 10, 11, 12, 13 are allowed.
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* These correspond to the C-BUS signals INT 0, 1, 2, 3, 41, 42, 5, 6
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* respectively. This is with the desktop C-BUS addin card.
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*
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* Hiroshi TSUKADA-san writes in FreeBSD98-testers that cbus IRQ
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* 6 is routed to the IRQ 7 pin of the pcic in pc98 cbus based
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* cards. I do not know how pc98 laptop models are wired.
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*/
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#ifdef PC98
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#define PCIC_INT_MASK_ALLOWED 0x3E68 /* PC98 */
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#else
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#define PCIC_INT_MASK_ALLOWED 0xDEB8 /* AT */
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#endif
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#define PCIC_IO_WIN 2
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#define PCIC_MEM_WIN 5
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#define PCIC_CARD_SLOTS 4
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#define PCIC_MAX_CARDS 2
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#define PCIC_MAX_SLOTS (PCIC_MAX_CARDS * PCIC_CARD_SLOTS)
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