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eaef5f0af8
OFW interrupt map interface to also return the device's interrupt parent. MFC after: 8.1-RELEASE
113 lines
3.4 KiB
C
113 lines
3.4 KiB
C
/*-
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* Copyright 2006 by Juniper Networks. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_OCP85XX_H_
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#define _MACHINE_OCP85XX_H_
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/*
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* Configuration control and status registers
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*/
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#define OCP85XX_CCSRBAR (CCSRBAR_VA + 0x0)
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#define OCP85XX_BPTR (CCSRBAR_VA + 0x20)
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/*
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* E500 Coherency Module registers
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*/
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#define OCP85XX_EEBPCR (CCSRBAR_VA + 0x1010)
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/*
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* Local access registers
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*/
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#define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x20 * (n))
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#define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc10 + 0x20 * (n))
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#define OCP85XX_TGTIF_PCI0 0
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#define OCP85XX_TGTIF_PCI1 1
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#define OCP85XX_TGTIF_PCI2 2
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#define OCP85XX_TGTIF_PCI3 3
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#define OCP85XX_TGTIF_LBC 4
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#define OCP85XX_TGTIF_RAM_INTL 11
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#define OCP85XX_TGTIF_RIO 12
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#define OCP85XX_TGTIF_RAM1 15
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#define OCP85XX_TGTIF_RAM2 22
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/*
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* L2 cache registers
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*/
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#define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000)
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/*
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* Power-On Reset configuration
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*/
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#define OCP85XX_PORDEVSR (CCSRBAR_VA + 0xe000c)
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#define OCP85XX_PORDEVSR2 (CCSRBAR_VA + 0xe0014)
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/*
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* Status Registers.
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*/
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#define OCP85XX_RSTCR (CCSRBAR_VA + 0xe00b0)
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/*
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* OCP Bus Definitions
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*/
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#define OCP85XX_I2C0_OFF 0x03000
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#define OCP85XX_I2C1_OFF 0x03100
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#define OCP85XX_I2C_SIZE 0x16
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#define OCP85XX_UART0_OFF 0x04500
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#define OCP85XX_UART1_OFF 0x04600
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#define OCP85XX_UART_SIZE 0x10
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#define OCP85XX_LBC_OFF 0x05000
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#define OCP85XX_LBC_SIZE 0x1000
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#define OCP85XX_PCI0_OFF 0x08000
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#define OCP85XX_PCI1_OFF 0x09000
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#define OCP85XX_PCI2_OFF 0x0A000
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#define OCP85XX_PCI3_OFF 0x0B000
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#define OCP85XX_PCI_SIZE 0x1000
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#define OCP85XX_TSEC0_OFF 0x24000
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#define OCP85XX_TSEC1_OFF 0x25000
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#define OCP85XX_TSEC2_OFF 0x26000
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#define OCP85XX_TSEC3_OFF 0x27000
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#define OCP85XX_TSEC_SIZE 0x1000
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#define OCP85XX_OPENPIC_OFF 0x40000
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#define OCP85XX_OPENPIC_SIZE 0x200B4
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#define OCP85XX_QUICC_OFF 0x80000
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#define OCP85XX_QUICC_SIZE 0x20000
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#define OCP85XX_SEC_OFF 0x30000
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#define OCP85XX_SEC_SIZE 0x10000
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/*
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* PIC definitions
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*/
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#define ISA_IRQ(n) (INTR_VEC(ATPIC_ID, n))
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#define PIC_IRQ_EXT(n) (INTR_VEC(OPIC_ID, (n)))
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#define PIC_IRQ_INT(n) (INTR_VEC(OPIC_ID, (16 + (n))))
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#endif /* _MACHINE_OCP85XX_H */
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