Paul Saab da0cc5d3ff Move the ciss quirk to the right section, also update the comment ... stating that the controllers do not support SYNC CACHE since ciss only supports a small subset of the scsi spec.		2003-12-08 06:29:38 +00:00
..
scsi	Move the ciss quirk to the right section, also update the comment	2003-12-08 06:29:38 +00:00
cam_ccb.h	Add a PATH_INQ flag, PIM_NO_6_BYTE, which indicates the SIM never wishes to	2003-07-28 06:15:59 +00:00
cam_debug.h
cam_periph.c	Don't be so chatty when performing manual sense. This should make ATAPICAM	2003-11-08 10:56:57 +00:00
cam_periph.h
cam_queue.c
cam_queue.h
cam_sim.c
cam_sim.h
cam_xpt_periph.h
cam_xpt_sim.h
cam_xpt.c	Sprinkle GIANT_REQUIRED asserts around the xpt layer to aid with locking the	2003-11-09 02:22:33 +00:00
cam_xpt.h
cam.c
cam.h