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1fa7f10bac
domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ |
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.. | ||
hwpmc_amd.c | ||
hwpmc_amd.h | ||
hwpmc_arm.c | ||
hwpmc_core.c | ||
hwpmc_core.h | ||
hwpmc_ia64.c | ||
hwpmc_intel.c | ||
hwpmc_logging.c | ||
hwpmc_mips24k.c | ||
hwpmc_mips24k.h | ||
hwpmc_mips.c | ||
hwpmc_mod.c | ||
hwpmc_pentium.c | ||
hwpmc_pentium.h | ||
hwpmc_piv.c | ||
hwpmc_piv.h | ||
hwpmc_powerpc.c | ||
hwpmc_ppro.c | ||
hwpmc_ppro.h | ||
hwpmc_sparc64.c | ||
hwpmc_tsc.c | ||
hwpmc_tsc.h | ||
hwpmc_uncore.c | ||
hwpmc_uncore.h | ||
hwpmc_x86.c | ||
hwpmc_xscale.c | ||
hwpmc_xscale.h | ||
pmc_events.h |