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2b3ad18853
The ci20 port (by kan@) is going to reuse almost all of the intrng code since the SoC in question looks suspiciously like someone took an ARM SoC design and replaced the ARM core with a MIPS core. * migrate out the code; * rename ARM_ -> INTR_; * rename arm_ -> intr_; * move the interrupt flush routine from intr.c / intrng.c into arm/machdep_intr.c - removing the code duplication and removing the ARM specific bits from here. Thanks to the Star Wars: The Force Awakens premiere line for allowing me a couple hours of quiet time to finish the universe builds. Tested: * make universe TODO: * The structure definitions in subr_intr.c still includes machine/intr.h which requires one duplicates all of the intrng definitions in the platform code (which kan has done, and I think we don't have to.) Instead I should break out the generic things (function declarations, common intr structures, etc) into a separate header. * Kan has requested I make the PIC based IPI stuff optional.
125 lines
3.0 KiB
Objective-C
125 lines
3.0 KiB
Objective-C
#-
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# Copyright (c) 2012 Jakub Wojciech Klama <jceel@FreeBSD.org>
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# Copyright (c) 2015 Svatopluk Kraus
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# Copyright (c) 2015 Michal Meloun
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# 1. Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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# SUCH DAMAGE.
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#
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# $FreeBSD$
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#
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#include <sys/bus.h>
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#include <sys/cpuset.h>
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#include <machine/frame.h>
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#include <machine/intr.h>
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INTERFACE pic;
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CODE {
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static int null_pic_bind(device_t dev, struct intr_irqsrc *isrc)
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{
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return (EOPNOTSUPP);
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}
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static void null_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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return;
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}
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static void null_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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return;
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}
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static void null_pic_init_secondary(device_t dev)
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{
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return;
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}
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static void null_pic_ipi_send(device_t dev, cpuset_t cpus, u_int ipi)
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{
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return;
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}
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};
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METHOD int register {
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device_t dev;
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struct intr_irqsrc *isrc;
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boolean_t *is_percpu;
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};
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METHOD int unregister {
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device_t dev;
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struct intr_irqsrc *isrc;
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};
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METHOD void disable_intr {
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device_t dev;
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struct intr_irqsrc *isrc;
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} DEFAULT null_pic_disable_intr;
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METHOD void disable_source {
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device_t dev;
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struct intr_irqsrc *isrc;
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};
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METHOD void enable_source {
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device_t dev;
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struct intr_irqsrc *isrc;
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};
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METHOD void enable_intr {
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device_t dev;
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struct intr_irqsrc *isrc;
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} DEFAULT null_pic_enable_intr;
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METHOD void pre_ithread {
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device_t dev;
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struct intr_irqsrc *isrc;
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};
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METHOD void post_ithread {
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device_t dev;
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struct intr_irqsrc *isrc;
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};
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METHOD void post_filter {
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device_t dev;
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struct intr_irqsrc *isrc;
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};
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METHOD int bind {
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device_t dev;
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struct intr_irqsrc *isrc;
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} DEFAULT null_pic_bind;
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METHOD void init_secondary {
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device_t dev;
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} DEFAULT null_pic_init_secondary;
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METHOD void ipi_send {
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device_t dev;
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struct intr_irqsrc *isrc;
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cpuset_t cpus;
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} DEFAULT null_pic_ipi_send;
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