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999da77859
freebsd/sys/dev/esp/ncr53c9xvar.h
Marius Strobl 85de9f54f8 o Move the MODULE_DEPEND() for cam(4) from the esp_sbus.c front-end to 
the ncr53c9x.c core where it actually belongs so future front-ends
  don't need to add it.
o Use the correct OFW property when looking for the initiator ID of the
  SBus device.
o Don't specify an alignment when creating the parent DMA tag for
  SUNW,fas; their DMA engine doesn't require an alignment constraint
  and it's no inherited by the child DMA tags anyway (which probably
  is a bug though).
o Drop the superfluous sc_maxsync and use sc_minsync instead. The
  former apparently was added due to a confusion with the maximum
  frequency used in cam(4), which basically corresponds to the
  inverse of minimum sync period.
o Merge ncr53c9x.c from NetBSD:
  1.116: NCRDMA_SETUP() should be called before NCR_SET_COUNT() and
         NCRCMD_DMA command in ncr53c9x_select().
  1.125: free allocated resources on detach.
o Static'ize ncr53c9x_action(), ncr53c9x_init() and ncr53c9x_reset()
  as these are not required outside of ncr53c9x.c.
o In ncr53c9x_attach() don't leak the device mutex in case attaching
  fails.
o Register an asynchronous notification handler so in case cam(4)
  reports a lost device we can cancel outstanding commands and
  restore the default parameters for the target in question.
o For FAS366 correctly support 16-bit target IDs and let it know
  that we use 32-bit transfers.
o Overhaul the negotiation of transfer settings. This includes
  distinguishing between current and goal transfer settings of the
  target so we can renegotiate their goal settings when necessary
  and correcting the order in which tagged, wide and synchronous
  transfers are negotiated.
o If we are requesting sense, force a renegotiation if we are
  currently using anything different from asynchronous at 8 bit
  as the target might have lost our transfer negotiations.
o In case of an XPT_RESET_BUS just directly call ncr53c9x_init()
  instead of issuing a NCRCMD_RSTSCSI, which in turn will issue an
  interrupt that is treated as an unexpected SCSI bus reset by
  ncr53c9x_intr() and thus calls ncr53c9x_init(). Remove the now
  no longer used ncr53c9x_scsi_reset().
o Correct an off-by-one error when setting cpi->max_lun.
o In replace printf(9) with device_printf(9) calls where appropriate
  and in ncr53c9x_action() remove some unnecessarily verbose messages.
o In ncr53c9x_sched() use TAILQ_FOREACH() instead of reimplementing
  it and consolidate two tagging-related target info checks into one.
o In ncr53c9x_done() set the CAM status to CAM_SCSI_STATUS_ERROR when
  appropriate, respect CAM_DIS_AUTOSENSE and teach it to return SCSI
  status information.
o In ncr53c9x_dequeue() ensure the tags are cleared.
o Use ulmin() instead of min() where appropriate.
o In ncr53c9x_msgout() consistently use the reset label.
o When we're interrupted during a data phase and the DMA engine is
  still active, don't panic but reset the core and the DMA engine as
  this should be sufficient. Also, the typical problem for triggering
  this was the lack of renegotiation when requesting sense.
o Correctly handle DEVICE RESETs.
o Adapt the locking of esp(4) to MPSAFE cam(4). This includes moving
  the calls of lsi64854_attach() to the bus front-ends so it can pass
  the esp(4) mutex to bus_dma_tag_create(9).
o Change the LSI64854 driver to not create a DMA tag and map for the
  Ethernet channel as le(4) will handle these on its own as well as
  sync and unload the DMA maps for the SCSI and parallel port channel
  after a DMA transfer.
o Cam(4)'ify some NetBSD-centric comments.
o Use bus_{read,write}_*(9) instead of bus_space_{read,write}_*(9)
  and take advantage of rman_get_rid(9) in order to save some softc
  members.

Reviewed by:	scottl
MFC after:	1 month
2008-09-08 20:20:44 +00:00

480 lines
16 KiB
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/* $NetBSD: ncr53c9xvar.h,v 1.46 2005/02/04 02:10:36 perry Exp $ */
/*-
* Copyright (c) 1997 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*-
* Copyright (c) 1994 Peter Galbavy. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Peter Galbavy.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* $FreeBSD$ */
#ifndef _DEV_IC_NCR53C9XVAR_H_
#define _DEV_IC_NCR53C9XVAR_H_
#include <sys/lock.h>
/* Set this to 1 for normal debug, or 2 for per-target tracing. */
/* #define NCR53C9X_DEBUG 2 */
/* Wide or differential can have 16 targets */
#define NCR_NLUN 8
#define NCR_ABORT_TIMEOUT 2000 /* time to wait for abort */
#define NCR_SENSE_TIMEOUT 1000 /* time to wait for sense */
#define FREQTOCCF(freq) (((freq + 4) / 5))
/*
* NCR 53c9x variants. Note these values are used as indexes into
* a table; do not modify them unless you know what you are doing.
*/
#define NCR_VARIANT_ESP100 0
#define NCR_VARIANT_ESP100A 1
#define NCR_VARIANT_ESP200 2
#define NCR_VARIANT_NCR53C94 3
#define NCR_VARIANT_NCR53C96 4
#define NCR_VARIANT_ESP406 5
#define NCR_VARIANT_FAS408 6
#define NCR_VARIANT_FAS216 7
#define NCR_VARIANT_AM53C974 8
#define NCR_VARIANT_FAS366 9
#define NCR_VARIANT_NCR53C90_86C01 10
#define NCR_VARIANT_FAS100A 11
#define NCR_VARIANT_FAS236 12
#define NCR_VARIANT_MAX 13
/* XXX Max tag depth. Should this be defined in the register header? */
#define NCR_TAG_DEPTH 256
/*
* ECB. Holds additional information for each SCSI command Comments: We
* need a separate scsi command block because we may need to overwrite it
* with a request sense command. Basicly, we refrain from fiddling with
* the ccb union (except do the expected updating of return values).
* We'll generally update: ccb->ccb_h.status and ccb->csio.{resid,
* scsi_status,sense_data}.
*/
struct ncr53c9x_ecb {
/* These fields are preserved between alloc and free */
struct ncr53c9x_softc *sc;
int tag_id;
int flags;
union ccb *ccb; /* SCSI xfer ctrl block from above */
TAILQ_ENTRY(ncr53c9x_ecb) free_links;
TAILQ_ENTRY(ncr53c9x_ecb) chain;
#define ECB_ALLOC 0x01
#define ECB_READY 0x02
#define ECB_SENSE 0x04
#define ECB_ABORT 0x40
#define ECB_RESET 0x80
#define ECB_TENTATIVE_DONE 0x100
int timeout;
struct callout ch;
struct {
u_char msg[3]; /* Selection Id msg and tags */
struct scsi_generic cmd; /* SCSI command block */
} cmd;
char *daddr; /* Saved data pointer */
int clen; /* Size of command in cmd.cmd */
int dleft; /* Residue */
u_char stat; /* SCSI status byte */
u_char tag[2]; /* TAG bytes */
u_char pad[1];
#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
char trace[1000];
#endif
};
#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
#define ECB_TRACE(ecb, msg, a, b) do { \
const char *f = "[" msg "]"; \
int n = strlen((ecb)->trace); \
if (n < (sizeof((ecb)->trace)-100)) \
sprintf((ecb)->trace + n, f, a, b); \
} while(0)
#else
#define ECB_TRACE(ecb, msg, a, b)
#endif
/*
* Some info about each (possible) target and LUN on the SCSI bus.
*
* SCSI I and II devices can have up to 8 LUNs, each with up to 256
* outstanding tags. SCSI III devices have 64-bit LUN identifiers
* that can be sparsely allocated.
*
* Since SCSI II devices can have up to 8 LUNs, we use an array
* of 8 pointers to ncr53c9x_linfo structures for fast lookup.
* Longer LUNs need to traverse the linked list.
*/
struct ncr53c9x_linfo {
int64_t lun;
LIST_ENTRY(ncr53c9x_linfo) link;
time_t last_used;
u_char used; /* # slots in use */
u_char avail; /* where to start scanning */
u_char busy;
struct ncr53c9x_ecb *untagged;
struct ncr53c9x_ecb *queued[NCR_TAG_DEPTH];
};
struct ncr53c9x_xinfo {
u_char period;
u_char offset;
u_char width;
};
struct ncr53c9x_tinfo {
int cmds; /* # of commands processed */
int dconns; /* # of disconnects */
int touts; /* # of timeouts */
int perrs; /* # of parity errors */
int senses; /* # of request sense commands sent */
u_char flags;
#define T_SYNCHOFF 0x01 /* SYNC mode is permanently off */
#define T_RSELECTOFF 0x02 /* RE-SELECT mode is off */
#define T_TAG 0x04 /* Turn on TAG QUEUEs */
#define T_SDTRSENT 0x08 /* SDTR message has been sent to */
#define T_WDTRSENT 0x10 /* WDTR message has been sent to */
struct ncr53c9x_xinfo curr;
struct ncr53c9x_xinfo goal;
LIST_HEAD(lun_list, ncr53c9x_linfo) luns;
struct ncr53c9x_linfo *lun[NCR_NLUN]; /* For speedy lookups */
};
/* Look up a lun in a tinfo */
#define TINFO_LUN(t, l) ( \
(((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) \
? ((t)->lun[(l)]) \
: ncr53c9x_lunsearch((t), (int64_t)(l)) \
)
/* Register a linenumber (for debugging) */
#define LOGLINE(p)
#define NCR_SHOWECBS 0x01
#define NCR_SHOWINTS 0x02
#define NCR_SHOWCMDS 0x04
#define NCR_SHOWMISC 0x08
#define NCR_SHOWTRAC 0x10
#define NCR_SHOWSTART 0x20
#define NCR_SHOWPHASE 0x40
#define NCR_SHOWDMA 0x80
#define NCR_SHOWCCMDS 0x100
#define NCR_SHOWMSGS 0x200
#ifdef NCR53C9X_DEBUG
extern int ncr53c9x_debug;
#define NCR_ECBS(str) \
do {if (ncr53c9x_debug & NCR_SHOWECBS) printf str;} while (0)
#define NCR_MISC(str) \
do {if (ncr53c9x_debug & NCR_SHOWMISC) printf str;} while (0)
#define NCR_INTS(str) \
do {if (ncr53c9x_debug & NCR_SHOWINTS) printf str;} while (0)
#define NCR_TRACE(str) \
do {if (ncr53c9x_debug & NCR_SHOWTRAC) printf str;} while (0)
#define NCR_CMDS(str) \
do {if (ncr53c9x_debug & NCR_SHOWCMDS) printf str;} while (0)
#define NCR_START(str) \
do {if (ncr53c9x_debug & NCR_SHOWSTART) printf str;}while (0)
#define NCR_PHASE(str) \
do {if (ncr53c9x_debug & NCR_SHOWPHASE) printf str;}while (0)
#define NCR_DMA(str) \
do {if (ncr53c9x_debug & NCR_SHOWDMA) printf str;}while (0)
#define NCR_MSGS(str) \
do {if (ncr53c9x_debug & NCR_SHOWMSGS) printf str;}while (0)
#else
#define NCR_ECBS(str)
#define NCR_MISC(str)
#define NCR_INTS(str)
#define NCR_TRACE(str)
#define NCR_CMDS(str)
#define NCR_START(str)
#define NCR_PHASE(str)
#define NCR_DMA(str)
#define NCR_MSGS(str)
#endif
#define NCR_MAX_MSG_LEN 8
struct ncr53c9x_softc;
/*
* Function switch used as glue to MD code.
*/
struct ncr53c9x_glue {
/* Mandatory entry points. */
u_char (*gl_read_reg)(struct ncr53c9x_softc *, int);
void (*gl_write_reg)(struct ncr53c9x_softc *, int, u_char);
int (*gl_dma_isintr)(struct ncr53c9x_softc *);
void (*gl_dma_reset)(struct ncr53c9x_softc *);
int (*gl_dma_intr)(struct ncr53c9x_softc *);
int (*gl_dma_setup)(struct ncr53c9x_softc *,
caddr_t *, size_t *, int, size_t *);
void (*gl_dma_go)(struct ncr53c9x_softc *);
void (*gl_dma_stop)(struct ncr53c9x_softc *);
int (*gl_dma_isactive)(struct ncr53c9x_softc *);
/* Optional entry points. */
void (*gl_clear_latched_intr)(struct ncr53c9x_softc *);
};
struct ncr53c9x_softc {
device_t sc_dev; /* us as a device */
struct cam_sim *sc_sim; /* our scsi adapter */
struct cam_path *sc_path; /* our scsi channel */
struct callout sc_watchdog; /* periodic timer */
const struct ncr53c9x_glue *sc_glue; /* glue to MD code */
int sc_cfflags; /* Copy of config flags */
/* register defaults */
u_char sc_cfg1; /* Config 1 */
u_char sc_cfg2; /* Config 2, not ESP100 */
u_char sc_cfg3; /* Config 3, ESP200,FAS */
u_char sc_cfg3_fscsi; /* Chip-specific FSCSI bit */
u_char sc_cfg4; /* Config 4, only ESP200 */
u_char sc_cfg5; /* Config 5, only ESP200 */
u_char sc_ccf; /* Clock Conversion */
u_char sc_timeout;
/* register copies, see espreadregs() */
u_char sc_espintr;
u_char sc_espstat;
u_char sc_espstep;
u_char sc_espstat2;
u_char sc_espfflags;
/* Lists of command blocks */
TAILQ_HEAD(ecb_list, ncr53c9x_ecb) ready_list;
struct ncr53c9x_ecb *sc_nexus; /* Current command */
int sc_ntarg;
struct ncr53c9x_tinfo *sc_tinfo;
/* Data about the current nexus (updated for every cmd switch) */
caddr_t sc_dp; /* Current data pointer */
ssize_t sc_dleft; /* Data left to transfer */
/* Adapter state */
int sc_phase; /* Copy of what bus phase we are in */
int sc_prevphase; /* Copy of what bus phase we were in */
u_char sc_state; /* State applicable to the adapter */
u_char sc_flags; /* See below */
u_char sc_selid;
u_char sc_lastcmd;
/* Message stuff */
u_short sc_msgify; /* IDENTIFY message associated with nexus */
u_short sc_msgout; /* What message is on its way out? */
u_short sc_msgpriq; /* One or more messages to send (encoded) */
u_short sc_msgoutq; /* What messages have been sent so far? */
u_char *sc_omess; /* MSGOUT buffer */
int sc_omess_self; /* MSGOUT buffer is self-allocated */
caddr_t sc_omp; /* Message pointer (for multibyte messages) */
size_t sc_omlen;
u_char *sc_imess; /* MSGIN buffer */
int sc_imess_self; /* MSGIN buffer is self-allocated */
caddr_t sc_imp; /* Message pointer (for multibyte messages) */
size_t sc_imlen;
caddr_t sc_cmdp; /* Command pointer (for DMAed commands) */
size_t sc_cmdlen; /* Size of command in transit */
/* Hardware attributes */
int sc_freq; /* SCSI bus frequency in MHz */
int sc_id; /* Our SCSI id */
int sc_rev; /* Chip revision */
int sc_features; /* Chip features */
int sc_minsync; /* Minimum sync period / 4 */
int sc_maxxfer; /* Maximum transfer size */
int sc_maxoffset; /* Maximum offset */
int sc_maxwidth; /* Maximum width */
int sc_extended_geom; /* Should we return extended geometry */
struct mtx sc_lock; /* driver mutex */
struct ncr53c9x_ecb *ecb_array;
TAILQ_HEAD(,ncr53c9x_ecb) free_list;
};
/* values for sc_state */
#define NCR_IDLE 1 /* Waiting for something to do */
#define NCR_SELECTING 2 /* SCSI command is arbiting */
#define NCR_RESELECTED 3 /* Has been reselected */
#define NCR_IDENTIFIED 4 /* Has gotten IFY but not TAG */
#define NCR_CONNECTED 5 /* Actively using the SCSI bus */
#define NCR_DISCONNECT 6 /* MSG_DISCONNECT received */
#define NCR_CMDCOMPLETE 7 /* MSG_CMDCOMPLETE received */
#define NCR_CLEANING 8
#define NCR_SBR 9 /* Expect a SCSI RST because we commanded it */
/* values for sc_flags */
#define NCR_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */
#define NCR_ABORTING 0x02 /* Bailing out */
#define NCR_ICCS 0x04 /* Expect status phase results */
#define NCR_WAITI 0x08 /* Waiting for non-DMA data to arrive */
#define NCR_ATN 0x10 /* ATN asserted */
#define NCR_EXPECT_ILLCMD 0x20 /* Expect Illegal Command Interrupt */
/* values for sc_features */
#define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */
#define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */
#define NCR_F_DMASELECT 0x04 /* can do dmaselect */
#define NCR_F_SELATN3 0x08 /* chip supports SELATN3 command */
/* values for sc_msgout */
#define SEND_DEV_RESET 0x0001
#define SEND_PARITY_ERROR 0x0002
#define SEND_INIT_DET_ERR 0x0004
#define SEND_REJECT 0x0008
#define SEND_IDENTIFY 0x0010
#define SEND_ABORT 0x0020
#define SEND_TAG 0x0040
#define SEND_WDTR 0x0080
#define SEND_SDTR 0x0100
/* SCSI Status codes */
#define ST_MASK 0x3e /* bit 0,6,7 is reserved */
/* phase bits */
#define IOI 0x01
#define CDI 0x02
#define MSGI 0x04
/* Information transfer phases */
#define DATA_OUT_PHASE (0)
#define DATA_IN_PHASE (IOI)
#define COMMAND_PHASE (CDI)
#define STATUS_PHASE (CDI | IOI)
#define MESSAGE_OUT_PHASE (MSGI | CDI)
#define MESSAGE_IN_PHASE (MSGI | CDI | IOI)
#define PHASE_MASK (MSGI | CDI | IOI)
/* Some pseudo phases for getphase()*/
#define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */
#define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */
#define PSEUDO_PHASE 0x100 /* "pseudo" bit */
/*
* Macros to read and write the chip's registers.
*/
#define NCR_READ_REG(sc, reg) \
(*(sc)->sc_glue->gl_read_reg)((sc), (reg))
#define NCR_WRITE_REG(sc, reg, val) \
(*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))
#ifdef NCR53C9X_DEBUG
#define NCRCMD(sc, cmd) do { \
if ((ncr53c9x_debug & NCR_SHOWCCMDS) != 0) \
printf("<CMD:0x%x %d>", (unsigned)cmd, __LINE__); \
sc->sc_lastcmd = cmd; \
NCR_WRITE_REG(sc, NCR_CMD, cmd); \
} while (0)
#else
#define NCRCMD(sc, cmd) NCR_WRITE_REG(sc, NCR_CMD, cmd)
#endif
/*
* Macros for locking
*/
#define NCR_LOCK_INIT(_sc) \
mtx_init(&(_sc)->sc_lock, "ncr", "ncr53c9x lock", MTX_DEF);
#define NCR_LOCK_INITIALIZED(_sc) mtx_initialized(&(_sc)->sc_lock)
#define NCR_LOCK(_sc) mtx_lock(&(_sc)->sc_lock)
#define NCR_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock)
#define NCR_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_lock, (_what))
#define NCR_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock)
/*
* DMA macros for NCR53c9x
*/
#define NCRDMA_ISINTR(sc) (*(sc)->sc_glue->gl_dma_isintr)((sc))
#define NCRDMA_RESET(sc) (*(sc)->sc_glue->gl_dma_reset)((sc))
#define NCRDMA_INTR(sc) (*(sc)->sc_glue->gl_dma_intr)((sc))
#define NCRDMA_SETUP(sc, addr, len, datain, dmasize) \
(*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize))
#define NCRDMA_GO(sc) (*(sc)->sc_glue->gl_dma_go)((sc))
#define NCRDMA_STOP(sc) (*(sc)->sc_glue->gl_dma_stop)((sc))
#define NCRDMA_ISACTIVE(sc) (*(sc)->sc_glue->gl_dma_isactive)((sc))
/*
* Macro to convert the chip register Clock Per Byte value to
* Synchronous Transfer Period.
*/
#define ncr53c9x_cpb2stp(sc, cpb) \
((250 * (cpb)) / (sc)->sc_freq)
int ncr53c9x_attach(struct ncr53c9x_softc *sc);
int ncr53c9x_detach(struct ncr53c9x_softc *sc);
void ncr53c9x_intr(void *arg);
#endif /* _DEV_IC_NCR53C9XVAR_H_ */
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