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The QUICC engine is found on various Freescale parts including MPC85xx, and provides multiple generic time-division serial channel resources, which are in turn muxed/demuxed by the Serial Communications Controller (SCC). Along with core QUICC/SCC functionality a uart(4)-compliant device driver is provided which allows for serial ports over QUICC/SCC. Approved by: cognet (mentor) Obtained from: Juniper MFp4: e500
152 lines
4.0 KiB
C
152 lines
4.0 KiB
C
/*-
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* Copyright (c) 2004-2006 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#define __RMAN_RESOURCE_VISIBLE
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/endian.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <sys/serial.h>
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#include <dev/scc/scc_bfe.h>
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#include <dev/scc/scc_bus.h>
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#include <dev/ic/quicc.h>
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#include "scc_if.h"
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#define quicc_read2(bas, reg) \
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bus_space_read_2((bas)->bst, (bas)->bsh, reg)
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#define quicc_write2(bas, reg, val) \
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bus_space_write_2((bas)->bst, (bas)->bsh, reg, val)
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static int quicc_bfe_attach(struct scc_softc *, int);
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static int quicc_bfe_enabled(struct scc_softc *, struct scc_chan *);
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static int quicc_bfe_iclear(struct scc_softc *, struct scc_chan *);
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static int quicc_bfe_ipend(struct scc_softc *);
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static int quicc_bfe_probe(struct scc_softc *);
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static kobj_method_t quicc_methods[] = {
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KOBJMETHOD(scc_attach, quicc_bfe_attach),
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KOBJMETHOD(scc_enabled, quicc_bfe_enabled),
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KOBJMETHOD(scc_iclear, quicc_bfe_iclear),
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KOBJMETHOD(scc_ipend, quicc_bfe_ipend),
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KOBJMETHOD(scc_probe, quicc_bfe_probe),
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{ 0, 0 }
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};
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struct scc_class scc_quicc_class = {
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"QUICC class",
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quicc_methods,
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sizeof(struct scc_softc),
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.cl_channels = 4,
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.cl_class = SCC_CLASS_QUICC,
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.cl_modes = SCC_MODE_ASYNC | SCC_MODE_BISYNC | SCC_MODE_HDLC,
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.cl_range = 0,
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};
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static int
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quicc_bfe_attach(struct scc_softc *sc, int reset)
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{
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struct scc_bas *bas;
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bas = &sc->sc_bas;
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return (0);
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}
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static int
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quicc_bfe_enabled(struct scc_softc *sc, struct scc_chan *ch)
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{
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struct scc_bas *bas;
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int unit;
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uint16_t val0, val1;
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bas = &sc->sc_bas;
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unit = ch->ch_nr - 1;
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val0 = quicc_read2(bas, QUICC_REG_SCC_TODR(unit));
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quicc_write2(bas, QUICC_REG_SCC_TODR(unit), ~val0);
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val1 = quicc_read2(bas, QUICC_REG_SCC_TODR(unit));
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quicc_write2(bas, QUICC_REG_SCC_TODR(unit), val0);
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return (((val0 | val1) == 0x8000) ? 1 : 0);
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}
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static int
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quicc_bfe_iclear(struct scc_softc *sc, struct scc_chan *ch)
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{
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return (0);
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}
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static int
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quicc_bfe_ipend(struct scc_softc *sc)
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{
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struct scc_bas *bas;
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struct scc_chan *ch;
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int c, ipend;
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uint16_t scce;
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bas = &sc->sc_bas;
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ipend = 0;
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for (c = 0; c < 4; c++) {
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ch = &sc->sc_chan[c];
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if (!ch->ch_enabled)
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continue;
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ch->ch_ipend = 0;
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mtx_lock_spin(&sc->sc_hwmtx);
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scce = quicc_read2(bas, QUICC_REG_SCC_SCCE(c));
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quicc_write2(bas, QUICC_REG_SCC_SCCE(c), ~0);
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mtx_unlock_spin(&sc->sc_hwmtx);
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if (scce & 0x0001)
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ch->ch_ipend |= SER_INT_RXREADY;
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if (scce & 0x0002)
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ch->ch_ipend |= SER_INT_TXIDLE;
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if (scce & 0x0004)
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ch->ch_ipend |= SER_INT_OVERRUN;
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if (scce & 0x0020)
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ch->ch_ipend |= SER_INT_BREAK;
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/* XXX SIGNALS */
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ipend |= ch->ch_ipend;
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}
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return (ipend);
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}
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static int
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quicc_bfe_probe(struct scc_softc *sc)
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{
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struct scc_bas *bas;
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bas = &sc->sc_bas;
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return (0);
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}
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