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76 lines
2.6 KiB
C
76 lines
2.6 KiB
C
/* $Id$ */
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/* $NetBSD: kftxxreg.h,v 1.4 1997/06/04 01:47:15 cgd Exp $ */
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/*
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* Copyright (c) 1997 by Matthew Jacob
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* NASA AMES Research Center.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Registers and values specific to KFTIA or KFTHA nodes.
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*/
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/*
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* Taken from combinations of:
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*
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* ``DWLPA and DWLPB PCI Adapter Technical Manual,
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* Order Number: EK-DWLPX-TM.A01''
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*
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* and
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*
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* ``AlphaServer 8200/8400 System Technical Manual,
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* Order Number EK-T8030-TM. A01''
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*/
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#define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
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/*
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* There are (potentially) 4 I/O hoses per I/O node.
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*
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* A CPU to Hose Address Mapping looks (roughly) like this:
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*
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* 39 38........36 35.34 33.................0
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* -------------------------------------------
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* |1|TLSB NodeID |Hose#|Hose Module Specific|
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* -------------------------------------------
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*
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*/
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#define HOSE_SIZE 0x400000000L
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#define MAXHOSE 4
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/*
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* Hose Specific I/O registers (offsets from base of I/O Board)
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*/
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#define KFT_IDPNSEX(hose) ((hose)? (0x2040 + (0x100 * (hose))) : 0x2A40)
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#define KFT_ICCNSE 0x2040
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#define KFT_ICCWTR 0x2100
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#define KFT_IDPMSR 0x2B80
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