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61d3f0bab2
monitored via CMCI, reset the interrupt threshold to 1 on resume. Reviewed by: jkim MFC after: 2 weeks
417 lines
12 KiB
C
417 lines
12 KiB
C
/*-
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* Copyright (c) 2001 Takanori Watanabe <takawata@jp.freebsd.org>
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* Copyright (c) 2001 Mitsuru IWASAKI <iwasaki@jp.freebsd.org>
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* Copyright (c) 2003 Peter Wemm
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* Copyright (c) 2008-2009 Jung-uk Kim <jkim@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/memrange.h>
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#include <sys/smp.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/intr_machdep.h>
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#include <machine/mca.h>
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#include <machine/pcb.h>
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#include <machine/pmap.h>
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#include <machine/specialreg.h>
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#ifdef SMP
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#include <machine/apicreg.h>
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#include <machine/smp.h>
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#include <machine/vmparam.h>
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#endif
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#include <contrib/dev/acpica/include/acpi.h>
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#include <dev/acpica/acpivar.h>
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#include "acpi_wakecode.h"
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#include "acpi_wakedata.h"
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/* Make sure the code is less than a page and leave room for the stack. */
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CTASSERT(sizeof(wakecode) < PAGE_SIZE - 1024);
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extern int acpi_resume_beep;
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extern int acpi_reset_video;
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#ifdef SMP
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extern struct xpcb **stopxpcbs;
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#else
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static struct xpcb **stopxpcbs;
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#endif
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int acpi_restorecpu(struct xpcb *, vm_offset_t);
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int acpi_savecpu(struct xpcb *);
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static void *acpi_alloc_wakeup_handler(void);
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static void acpi_stop_beep(void *);
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#ifdef SMP
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static int acpi_wakeup_ap(struct acpi_softc *, int);
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static void acpi_wakeup_cpus(struct acpi_softc *, cpumask_t);
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#endif
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#define WAKECODE_VADDR(sc) ((sc)->acpi_wakeaddr + (3 * PAGE_SIZE))
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#define WAKECODE_PADDR(sc) ((sc)->acpi_wakephys + (3 * PAGE_SIZE))
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#define WAKECODE_FIXUP(offset, type, val) do { \
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type *addr; \
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addr = (type *)(WAKECODE_VADDR(sc) + offset); \
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*addr = val; \
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} while (0)
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/* Turn off bits 1&2 of the PIT, stopping the beep. */
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static void
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acpi_stop_beep(void *arg)
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{
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outb(0x61, inb(0x61) & ~0x3);
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}
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#ifdef SMP
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static int
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acpi_wakeup_ap(struct acpi_softc *sc, int cpu)
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{
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int vector = (WAKECODE_PADDR(sc) >> 12) & 0xff;
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int apic_id = cpu_apic_ids[cpu];
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int ms;
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WAKECODE_FIXUP(wakeup_xpcb, struct xpcb *, stopxpcbs[cpu]);
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WAKECODE_FIXUP(wakeup_gdt, uint16_t, stopxpcbs[cpu]->xpcb_gdt.rd_limit);
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WAKECODE_FIXUP(wakeup_gdt + 2, uint64_t,
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stopxpcbs[cpu]->xpcb_gdt.rd_base);
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WAKECODE_FIXUP(wakeup_cpu, int, cpu);
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/* do an INIT IPI: assert RESET */
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lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
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APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
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/* wait for pending status end */
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lapic_ipi_wait(-1);
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/* do an INIT IPI: deassert RESET */
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lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL |
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APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0);
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/* wait for pending status end */
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DELAY(10000); /* wait ~10mS */
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lapic_ipi_wait(-1);
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/*
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* next we do a STARTUP IPI: the previous INIT IPI might still be
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* latched, (P5 bug) this 1st STARTUP would then terminate
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* immediately, and the previously started INIT IPI would continue. OR
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* the previous INIT IPI has already run. and this STARTUP IPI will
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* run. OR the previous INIT IPI was ignored. and this STARTUP IPI
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* will run.
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*/
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/* do a STARTUP IPI */
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lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
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APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
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vector, apic_id);
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lapic_ipi_wait(-1);
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DELAY(200); /* wait ~200uS */
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/*
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* finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
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* the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
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* this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
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* recognized after hardware RESET or INIT IPI.
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*/
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lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
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APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
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vector, apic_id);
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lapic_ipi_wait(-1);
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DELAY(200); /* wait ~200uS */
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/* Wait up to 5 seconds for it to start. */
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for (ms = 0; ms < 5000; ms++) {
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if (*(int *)(WAKECODE_VADDR(sc) + wakeup_cpu) == 0)
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return (1); /* return SUCCESS */
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DELAY(1000);
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}
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return (0); /* return FAILURE */
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}
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#define WARMBOOT_TARGET 0
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#define WARMBOOT_OFF (KERNBASE + 0x0467)
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#define WARMBOOT_SEG (KERNBASE + 0x0469)
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#define CMOS_REG (0x70)
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#define CMOS_DATA (0x71)
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#define BIOS_RESET (0x0f)
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#define BIOS_WARM (0x0a)
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static void
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acpi_wakeup_cpus(struct acpi_softc *sc, cpumask_t wakeup_cpus)
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{
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uint32_t mpbioswarmvec;
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cpumask_t map;
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int cpu;
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u_char mpbiosreason;
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/* save the current value of the warm-start vector */
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mpbioswarmvec = *((uint32_t *)WARMBOOT_OFF);
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outb(CMOS_REG, BIOS_RESET);
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mpbiosreason = inb(CMOS_DATA);
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/* setup a vector to our boot code */
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*((volatile u_short *)WARMBOOT_OFF) = WARMBOOT_TARGET;
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*((volatile u_short *)WARMBOOT_SEG) = WAKECODE_PADDR(sc) >> 4;
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outb(CMOS_REG, BIOS_RESET);
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outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
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/* Wake up each AP. */
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for (cpu = 1; cpu < mp_ncpus; cpu++) {
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map = 1ul << cpu;
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if ((wakeup_cpus & map) != map)
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continue;
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if (acpi_wakeup_ap(sc, cpu) == 0) {
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/* restore the warmstart vector */
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*(uint32_t *)WARMBOOT_OFF = mpbioswarmvec;
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panic("acpi_wakeup: failed to resume AP #%d (PHY #%d)",
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cpu, cpu_apic_ids[cpu]);
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}
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}
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/* restore the warmstart vector */
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*(uint32_t *)WARMBOOT_OFF = mpbioswarmvec;
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outb(CMOS_REG, BIOS_RESET);
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outb(CMOS_DATA, mpbiosreason);
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}
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#endif
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int
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acpi_sleep_machdep(struct acpi_softc *sc, int state)
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{
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struct savefpu *stopfpu;
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#ifdef SMP
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cpumask_t wakeup_cpus;
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#endif
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register_t cr3, rf;
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ACPI_STATUS status;
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int ret;
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ret = -1;
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if (sc->acpi_wakeaddr == 0ul)
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return (ret);
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#ifdef SMP
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wakeup_cpus = PCPU_GET(other_cpus);
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#endif
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AcpiSetFirmwareWakingVector(WAKECODE_PADDR(sc));
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rf = intr_disable();
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intr_suspend();
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/*
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* Temporarily switch to the kernel pmap because it provides
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* an identity mapping (setup at boot) for the low physical
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* memory region containing the wakeup code.
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*/
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cr3 = rcr3();
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load_cr3(KPML4phys);
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stopfpu = &stopxpcbs[0]->xpcb_pcb.pcb_user_save;
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if (acpi_savecpu(stopxpcbs[0])) {
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fpugetregs(curthread, stopfpu);
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#ifdef SMP
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if (wakeup_cpus != 0 && suspend_cpus(wakeup_cpus) == 0) {
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device_printf(sc->acpi_dev,
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"Failed to suspend APs: CPU mask = 0x%jx\n",
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(uintmax_t)(wakeup_cpus & ~stopped_cpus));
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goto out;
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}
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#endif
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WAKECODE_FIXUP(resume_beep, uint8_t, (acpi_resume_beep != 0));
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WAKECODE_FIXUP(reset_video, uint8_t, (acpi_reset_video != 0));
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WAKECODE_FIXUP(wakeup_xpcb, struct xpcb *, stopxpcbs[0]);
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WAKECODE_FIXUP(wakeup_gdt, uint16_t,
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stopxpcbs[0]->xpcb_gdt.rd_limit);
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WAKECODE_FIXUP(wakeup_gdt + 2, uint64_t,
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stopxpcbs[0]->xpcb_gdt.rd_base);
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WAKECODE_FIXUP(wakeup_cpu, int, 0);
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/* Call ACPICA to enter the desired sleep state */
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if (state == ACPI_STATE_S4 && sc->acpi_s4bios)
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status = AcpiEnterSleepStateS4bios();
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else
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status = AcpiEnterSleepState(state);
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if (status != AE_OK) {
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device_printf(sc->acpi_dev,
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"AcpiEnterSleepState failed - %s\n",
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AcpiFormatException(status));
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goto out;
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}
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for (;;)
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ia32_pause();
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} else {
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fpusetregs(curthread, stopfpu);
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#ifdef SMP
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if (wakeup_cpus != 0)
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acpi_wakeup_cpus(sc, wakeup_cpus);
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#endif
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acpi_resync_clock(sc);
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ret = 0;
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}
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out:
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#ifdef SMP
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if (wakeup_cpus != 0)
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restart_cpus(wakeup_cpus);
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#endif
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load_cr3(cr3);
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mca_resume();
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intr_resume();
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intr_restore(rf);
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AcpiSetFirmwareWakingVector(0);
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if (ret == 0 && mem_range_softc.mr_op != NULL &&
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mem_range_softc.mr_op->reinit != NULL)
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mem_range_softc.mr_op->reinit(&mem_range_softc);
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/* If we beeped, turn it off after a delay. */
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if (acpi_resume_beep)
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timeout(acpi_stop_beep, NULL, 3 * hz);
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return (ret);
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}
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static void *
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acpi_alloc_wakeup_handler(void)
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{
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void *wakeaddr;
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int i;
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/*
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* Specify the region for our wakeup code. We want it in the low 1 MB
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* region, excluding real mode IVT (0-0x3ff), BDA (0x400-0x4ff), EBDA
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* (less than 128KB, below 0xa0000, must be excluded by SMAP and DSDT),
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* and ROM area (0xa0000 and above). The temporary page tables must be
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* page-aligned.
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*/
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wakeaddr = contigmalloc(4 * PAGE_SIZE, M_DEVBUF, M_NOWAIT, 0x500,
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0xa0000, PAGE_SIZE, 0ul);
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if (wakeaddr == NULL) {
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printf("%s: can't alloc wake memory\n", __func__);
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return (NULL);
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}
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stopxpcbs = malloc(mp_ncpus * sizeof(*stopxpcbs), M_DEVBUF, M_WAITOK);
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for (i = 0; i < mp_ncpus; i++)
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stopxpcbs[i] = malloc(sizeof(**stopxpcbs), M_DEVBUF, M_WAITOK);
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return (wakeaddr);
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}
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void
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acpi_install_wakeup_handler(struct acpi_softc *sc)
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{
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static void *wakeaddr = NULL;
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uint64_t *pt4, *pt3, *pt2;
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int i;
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if (wakeaddr != NULL)
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return;
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wakeaddr = acpi_alloc_wakeup_handler();
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if (wakeaddr == NULL)
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return;
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sc->acpi_wakeaddr = (vm_offset_t)wakeaddr;
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sc->acpi_wakephys = vtophys(wakeaddr);
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bcopy(wakecode, (void *)WAKECODE_VADDR(sc), sizeof(wakecode));
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/* Patch GDT base address, ljmp targets and page table base address. */
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WAKECODE_FIXUP((bootgdtdesc + 2), uint32_t,
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WAKECODE_PADDR(sc) + bootgdt);
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WAKECODE_FIXUP((wakeup_sw32 + 2), uint32_t,
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WAKECODE_PADDR(sc) + wakeup_32);
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WAKECODE_FIXUP((wakeup_sw64 + 1), uint32_t,
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WAKECODE_PADDR(sc) + wakeup_64);
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WAKECODE_FIXUP(wakeup_pagetables, uint32_t, sc->acpi_wakephys);
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/* Save pointers to some global data. */
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WAKECODE_FIXUP(wakeup_retaddr, void *, acpi_restorecpu);
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WAKECODE_FIXUP(wakeup_kpml4, uint64_t, KPML4phys);
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WAKECODE_FIXUP(wakeup_ctx, vm_offset_t,
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WAKECODE_VADDR(sc) + wakeup_ctx);
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WAKECODE_FIXUP(wakeup_efer, uint64_t, rdmsr(MSR_EFER));
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WAKECODE_FIXUP(wakeup_pat, uint64_t, rdmsr(MSR_PAT));
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WAKECODE_FIXUP(wakeup_star, uint64_t, rdmsr(MSR_STAR));
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WAKECODE_FIXUP(wakeup_lstar, uint64_t, rdmsr(MSR_LSTAR));
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WAKECODE_FIXUP(wakeup_cstar, uint64_t, rdmsr(MSR_CSTAR));
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WAKECODE_FIXUP(wakeup_sfmask, uint64_t, rdmsr(MSR_SF_MASK));
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/* Build temporary page tables below realmode code. */
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pt4 = wakeaddr;
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pt3 = pt4 + (PAGE_SIZE) / sizeof(uint64_t);
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pt2 = pt3 + (PAGE_SIZE) / sizeof(uint64_t);
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/* Create the initial 1GB replicated page tables */
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for (i = 0; i < 512; i++) {
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/*
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* Each slot of the level 4 pages points
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* to the same level 3 page
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*/
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pt4[i] = (uint64_t)(sc->acpi_wakephys + PAGE_SIZE);
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pt4[i] |= PG_V | PG_RW | PG_U;
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/*
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* Each slot of the level 3 pages points
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* to the same level 2 page
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*/
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pt3[i] = (uint64_t)(sc->acpi_wakephys + (2 * PAGE_SIZE));
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pt3[i] |= PG_V | PG_RW | PG_U;
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/* The level 2 page slots are mapped with 2MB pages for 1GB. */
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pt2[i] = i * (2 * 1024 * 1024);
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pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
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}
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if (bootverbose)
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device_printf(sc->acpi_dev, "wakeup code va %p pa %p\n",
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(void *)sc->acpi_wakeaddr, (void *)sc->acpi_wakephys);
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}
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