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82 lines
3.5 KiB
Diff
82 lines
3.5 KiB
Diff
Pull in r199187 from upstream llvm trunk (by Jakob Stoklund Olesen):
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Always let value types influence register classes.
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When creating a virtual register for a def, the value type should be
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used to pick the register class. If we only use the register class
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constraint on the instruction, we might pick a too large register class.
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Some registers can store values of different sizes. For example, the x86
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xmm registers can hold f32, f64, and 128-bit vectors. The three
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different value sizes are represented by register classes with identical
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register sets: FR32, FR64, and VR128. These register classes have
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different spill slot sizes, so it is important to use the right one.
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The register class constraint on an instruction doesn't necessarily care
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about the size of the value its defining. The value type determines
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that.
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This fixes a problem where InstrEmitter was picking 32-bit register
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classes for 64-bit values on SPARC.
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Introduced here: http://svnweb.freebsd.org/changeset/base/262261
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Index: test/CodeGen/SPARC/spillsize.ll
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===================================================================
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--- test/CodeGen/SPARC/spillsize.ll
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+++ test/CodeGen/SPARC/spillsize.ll
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@@ -0,0 +1,25 @@
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+; RUN: llc < %s -verify-machineinstrs | FileCheck %s
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+target datalayout = "E-m:e-i64:64-n32:64-S128"
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+target triple = "sparcv9"
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+
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+; CHECK-LABEL: spill4
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+; This function spills two values: %p and the materialized large constant.
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+; Both must use 8-byte spill and fill instructions.
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+; CHECK: stx %{{..}}, [%fp+
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+; CHECK: stx %{{..}}, [%fp+
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+; CHECK: ldx [%fp+
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+; CHECK: ldx [%fp+
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+define void @spill4(i64* nocapture %p) {
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+entry:
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+ %val0 = load i64* %p
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+ %cmp0 = icmp ult i64 %val0, 385672958347594845
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+ %cm80 = zext i1 %cmp0 to i64
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+ store i64 %cm80, i64* %p, align 8
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+ tail call void asm sideeffect "", "~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{g2},~{g3},~{g4},~{g5},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o7}"()
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+ %arrayidx1 = getelementptr inbounds i64* %p, i64 1
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+ %val = load i64* %arrayidx1
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+ %cmp = icmp ult i64 %val, 385672958347594845
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+ %cm8 = select i1 %cmp, i64 10, i64 20
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+ store i64 %cm8, i64* %arrayidx1, align 8
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+ ret void
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+}
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Index: lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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===================================================================
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--- lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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+++ lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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@@ -220,10 +220,19 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *
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unsigned VRBase = 0;
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const TargetRegisterClass *RC =
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TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
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- // If the register class is unknown for the given definition, then try to
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- // infer one from the value type.
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- if (!RC && i < NumResults)
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- RC = TLI->getRegClassFor(Node->getSimpleValueType(i));
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+ // Always let the value type influence the used register class. The
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+ // constraints on the instruction may be too lax to represent the value
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+ // type correctly. For example, a 64-bit float (X86::FR64) can't live in
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+ // the 32-bit float super-class (X86::FR32).
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+ if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
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+ const TargetRegisterClass *VTRC =
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+ TLI->getRegClassFor(Node->getSimpleValueType(i));
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+ if (RC)
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+ VTRC = TRI->getCommonSubClass(RC, VTRC);
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+ if (VTRC)
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+ RC = VTRC;
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+ }
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+
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if (II.OpInfo[i].isOptionalDef()) {
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// Optional def must be a physical register.
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unsigned NumResults = CountResults(Node);
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