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6c56727456
return through doreti to handle ast's. This is necessary for the clock interrupts to work properly. - Change the clock interrupts on the x86 to be fast instead of threaded. This is needed because both hardclock() and statclock() need to run in the context of the current process, not in a separate thread context. - Kill the prevproc hack as it is no longer needed. - We really need Giant when we call psignal(), but we don't want to block during the clock interrupt. Instead, use two p_flag's in the proc struct to mark the current process as having a pending SIGVTALRM or a SIGPROF and let them be delivered during ast() when hardclock() has finished running. - Remove CLKF_BASEPRI, which was #ifdef'd out on the x86 anyways. It was broken on the x86 if it was turned on since cpl is gone. It's only use was to bogusly run softclock() directly during hardclock() rather than scheduling an SWI. - Remove the COM_LOCK simplelock and replace it with a clock_lock spin mutex. Since the spin mutex already handles disabling/restoring interrupts appropriately, this also lets us axe all the *_intr() fu. - Back out the hacks in the APIC_IO x86 cpu_initclocks() code to use temporary fast interrupts for the APIC trial. - Add two new process flags P_ALRMPEND and P_PROFPEND to mark the pending signals in hardclock() that are to be delivered in ast(). Submitted by: jakeb (making statclock safe in a fast interrupt) Submitted by: cp (concept of delaying signals until ast())
339 lines
8.6 KiB
C
339 lines
8.6 KiB
C
/*
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* Copyright (c) 1996, by Steve Passe
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_SMPTESTS_H_
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#define _MACHINE_SMPTESTS_H_
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/*
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* Various 'tests in progress' and configuration parameters.
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*/
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/*
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* Tor's clock improvements.
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*
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* When the giant kernel lock disappears, a different strategy should
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* probably be used, thus this patch can only be considered a temporary
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* measure.
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*
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* This patch causes (NCPU-1)*(128+100) extra IPIs per second.
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* During profiling, the number is (NCPU-1)*(1024+100) extra IPIs/s
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* in addition to extra IPIs due to forwarding ASTs to other CPUs.
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*
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* Having a shared AST flag in an SMP configuration is wrong, and I've
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* just kludged around it, based upon the kernel lock blocking other
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* processors from entering the kernel while handling an AST for one
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* processor. When the giant kernel lock disappers, this kludge breaks.
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*
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* -- Tor
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*/
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#define BETTER_CLOCK
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/*
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* Control the "giant lock" pushdown by logical steps.
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*/
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#define PUSHDOWN_LEVEL_1
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#define PUSHDOWN_LEVEL_2
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#define PUSHDOWN_LEVEL_3_NOT
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#define PUSHDOWN_LEVEL_4_NOT
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/*
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* Debug version of simple_lock. This will store the CPU id of the
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* holding CPU along with the lock. When a CPU fails to get the lock
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* it compares its own id to the holder id. If they are the same it
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* panic()s, as simple locks are binary, and this would cause a deadlock.
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*
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*/
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#define SL_DEBUG
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/*
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* Put FAST_INTR() ISRs at an APIC priority above the regular INTs.
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* Allow the mp_lock() routines to handle FAST interrupts while spinning.
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*/
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#ifdef PUSHDOWN_LEVEL_1
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#define FAST_HI
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#endif
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/*
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* These defines enable critical region locking of areas that were
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* protected via cli/sti in the UP kernel.
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*
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* COMLOCK protects the sio/cy drivers.
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* known to be incomplete:
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* joystick lkm
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* ?
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*/
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#ifdef PUSHDOWN_LEVEL_1
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#define USE_COMLOCK
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#endif
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/*
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* INTR_SIMPLELOCK has been removed, as the interrupt mechanism will likely
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* not use this sort of optimization if we move to interrupt threads.
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*/
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#ifdef PUSHDOWN_LEVEL_4
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#endif
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/*
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* CPL_AND_CML has been removed. Interrupt threads will eventually not
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* use either mechanism so there is no point trying to optimize it.
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*/
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#ifdef PUSHDOWN_LEVEL_3
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#endif
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/*
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* SPL_DEBUG_POSTCODE/INTR_SPL/SPL_DEBUG - removed
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*
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* These functions were too expensive for the standard case but, more
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* importantly, we should be able to come up with a much cleaner way
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* to handle the cpl. Having to do any locking at all is a mistake
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* for something that is modified as often as cpl is.
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*/
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/*
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* FAST_WITHOUTCPL - now made the default (define removed). Text below
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* contains the current discussion. I am confident we can find a solution
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* that does not require us to process softints from a hard int, which can
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* kill serial performance due to the lack of true hardware ipl's.
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*
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****
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*
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* Ignore the ipending bits when exiting FAST_INTR() routines.
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*
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* according to Bruce:
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*
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* setsoft*() may set ipending. setsofttty() is actually used in the
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* FAST_INTR handler in some serial drivers. This is necessary to get
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* output completions and other urgent events handled as soon as possible.
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* The flag(s) could be set in a variable other than ipending, but they
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* needs to be checked against cpl to decide whether the software interrupt
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* handler can/should run.
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*
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* (FAST_INTR used to just return
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* in all cases until rev.1.7 of vector.s. This worked OK provided there
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* were no user-mode CPU hogs. CPU hogs caused an average latency of 1/2
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* clock tick for output completions...)
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***
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*
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* So I need to restore cpl handling someday, but AFTER
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* I finish making spl/cpl MP-safe.
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*/
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#ifdef PUSHDOWN_LEVEL_1
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#endif
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/*
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* FAST_SIMPLELOCK no longer exists, because it doesn't help us. The cpu
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* is likely to already hold the MP lock and recursive MP locks are now
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* very cheap, so we do not need this optimization. Eventually *ALL*
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* interrupts will run in their own thread, so there is no sense complicating
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* matters now.
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*/
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#ifdef PUSHDOWN_LEVEL_1
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#endif
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/*
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* Portions of the old TEST_LOPRIO code, back from the grave!
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*/
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#define GRAB_LOPRIO
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/*
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* Send CPUSTOP IPI for stop/restart of other CPUs on DDB break.
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*/
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#define VERBOSE_CPUSTOP_ON_DDBBREAK
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#define CPUSTOP_ON_DDBBREAK
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/*
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* Bracket code/comments relevant to the current 'giant lock' model.
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* Everything is now the 'giant lock' model, but we will use this as
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* we start to "push down" the lock.
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*/
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#define GIANT_LOCK
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#ifdef APIC_IO
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/*
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* Enable extra counters for some selected locations in the interrupt handlers.
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* Look in apic_vector.s, apic_ipl.s and ipl.s for APIC_ITRACE or
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* APIC_INTR_DIAGNOSTIC.
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*/
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#undef APIC_INTR_DIAGNOSTIC
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/*
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* Add extra tracking of a specific interrupt. Look in apic_vector.s,
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* apic_ipl.s and ipl.s for APIC_ITRACE and log_intr_event.
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* APIC_INTR_DIAGNOSTIC must be defined for this to work.
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*/
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#ifdef APIC_INTR_DIAGNOSTIC
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#define APIC_INTR_DIAGNOSTIC_IRQ 17
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#endif
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/*
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* Don't assume that slow interrupt handler X is called from vector
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* X + ICU_OFFSET.
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*/
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#define APIC_INTR_REORDER
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/*
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* Redirect clock interrupts to a higher priority (fast intr) vector,
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* while still using the slow interrupt handler. Only effective when
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* APIC_INTR_REORDER is defined.
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*/
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#define APIC_INTR_HIGHPRI_CLOCK
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#endif /* APIC_IO */
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/*
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* Misc. counters.
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*
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#define COUNT_XINVLTLB_HITS
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*/
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/**
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* Hack to "fake-out" kernel into thinking it is running on a 'default config'.
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*
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* value == default type
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#define TEST_DEFAULT_CONFIG 6
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*/
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/*
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* Simple test code for IPI interaction, save for future...
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*
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#define TEST_TEST1
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#define IPI_TARGET_TEST1 1
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*/
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/*
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* Address of POST hardware port.
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* Defining this enables POSTCODE macros.
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*
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#define POST_ADDR 0x80
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*/
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/*
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* POST hardware macros.
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*/
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#ifdef POST_ADDR
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#define ASMPOSTCODE_INC \
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pushl %eax ; \
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movl _current_postcode, %eax ; \
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incl %eax ; \
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andl $0xff, %eax ; \
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movl %eax, _current_postcode ; \
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outb %al, $POST_ADDR ; \
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popl %eax
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/*
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* Overwrite the current_postcode value.
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*/
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#define ASMPOSTCODE(X) \
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pushl %eax ; \
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movl $X, %eax ; \
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movl %eax, _current_postcode ; \
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outb %al, $POST_ADDR ; \
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popl %eax
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/*
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* Overwrite the current_postcode low nibble.
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*/
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#define ASMPOSTCODE_LO(X) \
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pushl %eax ; \
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movl _current_postcode, %eax ; \
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andl $0xf0, %eax ; \
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orl $X, %eax ; \
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movl %eax, _current_postcode ; \
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outb %al, $POST_ADDR ; \
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popl %eax
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/*
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* Overwrite the current_postcode high nibble.
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*/
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#define ASMPOSTCODE_HI(X) \
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pushl %eax ; \
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movl _current_postcode, %eax ; \
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andl $0x0f, %eax ; \
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orl $(X<<4), %eax ; \
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movl %eax, _current_postcode ; \
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outb %al, $POST_ADDR ; \
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popl %eax
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#else
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#define ASMPOSTCODE_INC
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#define ASMPOSTCODE(X)
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#define ASMPOSTCODE_LO(X)
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#define ASMPOSTCODE_HI(X)
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#endif /* POST_ADDR */
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/*
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* These are all temps for debugging...
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*
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#define GUARD_INTS
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*/
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/*
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* This macro traps unexpected INTs to a specific CPU, eg. GUARD_CPU.
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*/
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#ifdef GUARD_INTS
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#define GUARD_CPU 1
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#define MAYBE_PANIC(irq_num) \
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cmpl $GUARD_CPU, _cpuid ; \
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jne 9f ; \
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cmpl $1, _ok_test1 ; \
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jne 9f ; \
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pushl lapic_isr3 ; \
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pushl lapic_isr2 ; \
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pushl lapic_isr1 ; \
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pushl lapic_isr0 ; \
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pushl lapic_irr3 ; \
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pushl lapic_irr2 ; \
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pushl lapic_irr1 ; \
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pushl lapic_irr0 ; \
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pushl $irq_num ; \
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pushl _cpuid ; \
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pushl $panic_msg ; \
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call _printf ; \
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addl $44, %esp ; \
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9:
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#else
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#define MAYBE_PANIC(irq_num)
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#endif /* GUARD_INTS */
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#endif /* _MACHINE_SMPTESTS_H_ */
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