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89 lines
3.9 KiB
C
89 lines
3.9 KiB
C
/*
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* Copyright (c) 1995, David Greenman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast
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* Ethernet driver
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*/
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/*
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* NOTE: Elements are ordered for optimal cacheline behavior, and NOT
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* for functional grouping.
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*/
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struct fxp_softc {
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struct arpcom arpcom; /* per-interface network data */
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struct resource *mem; /* resource descriptor for registers */
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struct resource *irq; /* resource descriptor for interrupt */
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void *ih; /* interrupt handler cookie */
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struct mtx sc_mtx;
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bus_space_tag_t sc_st; /* bus space tag */
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bus_space_handle_t sc_sh; /* bus space handle */
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struct mbuf *rfa_headm; /* first mbuf in receive frame area */
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struct mbuf *rfa_tailm; /* last mbuf in receive frame area */
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struct fxp_cb_tx *cbl_first; /* first active TxCB in list */
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int tx_queued; /* # of active TxCB's */
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int need_mcsetup; /* multicast filter needs programming */
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struct fxp_cb_tx *cbl_last; /* last active TxCB in list */
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struct fxp_stats *fxp_stats; /* Pointer to interface stats */
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int rx_idle_secs; /* # of seconds RX has been idle */
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struct callout_handle stat_ch; /* Handle for canceling our stat timeout */
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struct fxp_cb_tx *cbl_base; /* base of TxCB list */
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struct fxp_cb_mcs *mcsp; /* Pointer to mcast setup descriptor */
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int all_mcasts; /* receive all multicasts */
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struct ifmedia sc_media; /* media information */
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int phy_primary_addr; /* address of primary PHY */
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int phy_primary_device; /* device type of primary PHY */
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int phy_10Mbps_only; /* PHY is 10Mbps-only device */
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int eeprom_size; /* size of serial EEPROM */
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int suspended; /* 0 = normal 1 = suspended (APM) */
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u_int32_t saved_maps[5]; /* pci data */
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u_int32_t saved_biosaddr;
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u_int8_t saved_intline;
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u_int8_t saved_cachelnsz;
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u_int8_t saved_lattimer;
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};
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/* Macros to ease CSR access. */
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#define CSR_READ_1(sc, reg) \
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bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
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#define CSR_READ_2(sc, reg) \
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bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
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#define CSR_READ_4(sc, reg) \
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bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
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#define CSR_WRITE_1(sc, reg, val) \
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bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
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#define CSR_WRITE_2(sc, reg, val) \
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bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
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#define CSR_WRITE_4(sc, reg, val) \
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bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
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#define sc_if arpcom.ac_if
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#define FXP_UNIT(_sc) (_sc)->arpcom.ac_if.if_unit
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#define FXP_LOCK(_sc) mtx_enter(&(_sc)->sc_mtx, MTX_DEF)
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#define FXP_UNLOCK(_sc) mtx_exit(&(_sc)->sc_mtx, MTX_DEF)
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