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the file so that this compiles without forward declarations of that data. (It is impossible to forward-declare static data in Gnu C. Declaring it as static is correct, but causes bogus warnings from gcc -Wredundant-decls. Declaring it as extern works, but causes correct warnings from gcc -pedantic and is undefined in ANSI C. We usually declare it as extern. Here it was once really extern, but botched staticization left it as static here and apparently- extern in a header file.) ---------------------------------------------------------------------- another system, such as NetBSD, CVS: then name the system in this line, otherwise delete it. CVS: Reviewed by: CVS: Before committing changes please have someone check your work and CVS: include their name here. If the change is trivial and you have not else; i.e., CVS: they sent us a patch or a new module, then include their name/email CVS: address here. If this is your work then delete this line. CVS: ---------------------------------------------------------------------- ----------------------------------------------------------------------
1030 lines
26 KiB
C
1030 lines
26 KiB
C
/*
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* Low-level subroutines for Cronyx-Sigma adapter.
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*
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* Copyright (C) 1994-95 Cronyx Ltd.
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* Author: Serge Vakulenko, <vak@cronyx.ru>
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*
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* This software is distributed with NO WARRANTIES, not even the implied
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* warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Authors grant any other persons or organisations permission to use
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* or modify this software as long as this message is kept with the software,
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* all derivative works or modified versions.
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*
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* Version 1.6, Wed May 31 16:03:20 MSD 1995
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*/
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#if defined (MSDOS) || defined (__MSDOS__)
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# include <string.h>
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# include <dos.h>
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# define inb(port) inportb(port)
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# define inw(port) inport(port)
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# define outb(port,b) outportb(port,b)
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# define outw(port,w) outport(port,w)
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# define vtophys(a) (((unsigned long)(a)>>12 & 0xffff0) +\
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((unsigned)(a) & 0xffff))
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# include "cronyx.h"
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# include "cxreg.h"
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#else
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# include <sys/param.h>
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# include <sys/systm.h>
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# include <sys/socket.h>
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# include <net/if.h>
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# include <vm/vm.h>
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# include <vm/vm_param.h>
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# include <vm/pmap.h>
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# ifndef __FreeBSD__
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# include <machine/inline.h>
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# endif
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# include <machine/cronyx.h>
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# include <i386/isa/cxreg.h>
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#endif
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#define DMA_MASK 0xd4 /* DMA mask register */
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#define DMA_MASK_CLEAR 0x04 /* DMA clear mask */
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#define DMA_MODE 0xd6 /* DMA mode register */
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#define DMA_MODE_MASTER 0xc0 /* DMA master mode */
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#define BYTE *(unsigned char*)&
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static unsigned char irqmask [] = {
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BCR0_IRQ_DIS, BCR0_IRQ_DIS, BCR0_IRQ_DIS, BCR0_IRQ_3,
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BCR0_IRQ_DIS, BCR0_IRQ_5, BCR0_IRQ_DIS, BCR0_IRQ_7,
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BCR0_IRQ_DIS, BCR0_IRQ_DIS, BCR0_IRQ_10, BCR0_IRQ_11,
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BCR0_IRQ_12, BCR0_IRQ_DIS, BCR0_IRQ_DIS, BCR0_IRQ_15,
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};
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static unsigned char dmamask [] = {
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BCR0_DMA_DIS, BCR0_DMA_DIS, BCR0_DMA_DIS, BCR0_DMA_DIS,
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BCR0_DMA_DIS, BCR0_DMA_5, BCR0_DMA_6, BCR0_DMA_7,
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};
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static long cx_rxbaud = CX_SPEED_DFLT; /* receiver baud rate */
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static long cx_txbaud = CX_SPEED_DFLT; /* transmitter baud rate */
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static int cx_univ_mode = M_ASYNC; /* univ. chan. mode: async or sync */
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static int cx_sync_mode = M_HDLC; /* sync. chan. mode: HDLC, Bisync or X.21 */
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static int cx_iftype = 0; /* univ. chan. interface: upper/lower */
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static cx_chan_opt_t chan_opt_dflt = { /* mode-independent options */
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{ /* cor4 */
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7, /* FIFO threshold, odd is better */
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0,
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0, /* don't detect 1 to 0 on CTS */
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1, /* detect 1 to 0 on CD */
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0, /* detect 1 to 0 on DSR */
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},
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{ /* cor5 */
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0, /* receive flow control FIFO threshold */
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0,
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0, /* don't detect 0 to 1 on CTS */
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1, /* detect 0 to 1 on CD */
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0, /* detect 0 to 1 on DSR */
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},
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{ /* rcor */
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0, /* dummy clock source */
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ENCOD_NRZ, /* NRZ mode */
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0, /* disable DPLL */
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0,
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0, /* transmit line value */
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},
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{ /* tcor */
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0,
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0, /* local loopback mode */
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0,
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1, /* external 1x clock mode */
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0,
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0, /* dummy transmit clock source */
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},
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};
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static cx_opt_async_t opt_async_dflt = { /* default async options */
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{ /* cor1 */
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8-1, /* 8-bit char length */
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0, /* don't ignore parity */
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PARM_NOPAR, /* no parity */
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PAR_EVEN, /* even parity */
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},
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{ /* cor2 */
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0, /* disable automatic DSR */
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1, /* enable automatic CTS */
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0, /* disable automatic RTS */
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0, /* no remote loopback */
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0,
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0, /* disable embedded cmds */
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0, /* disable XON/XOFF */
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0, /* disable XANY */
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},
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{ /* cor3 */
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STOPB_1, /* 1 stop bit */
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0,
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0, /* disable special char detection */
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FLOWCC_PASS, /* pass flow ctl chars to the host */
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0, /* range detect disable */
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0, /* disable extended spec. char detect */
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},
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{ /* cor6 */
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PERR_INTR, /* generate exception on parity errors */
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BRK_INTR, /* generate exception on break condition */
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0, /* don't translate NL to CR on input */
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0, /* don't translate CR to NL on input */
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0, /* don't discard CR on input */
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},
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{ /* cor7 */
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0, /* don't translate CR to NL on output */
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0, /* don't translate NL to CR on output */
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0,
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0, /* don't process flow ctl err chars */
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0, /* disable LNext option */
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0, /* don't strip 8 bit on input */
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},
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0, 0, 0, 0, 0, 0, 0, /* clear schr1-4, scrl, scrh, lnxt */
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};
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static cx_opt_hdlc_t opt_hdlc_dflt = { /* default hdlc options */
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{ /* cor1 */
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2, /* 2 inter-frame flags */
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0, /* no-address mode */
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CLRDET_DISABLE, /* disable clear detect */
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AFLO_1OCT, /* 1-byte address field length */
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},
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{ /* cor2 */
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0, /* disable automatic DSR */
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0, /* disable automatic CTS */
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0, /* disable automatic RTS */
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0,
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CRC_INVERT, /* use CRC V.41 */
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0,
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FCS_NOTPASS, /* don't pass received CRC to the host */
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0,
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},
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{ /* cor3 */
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0, /* 0 pad characters sent */
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IDLE_FLAG, /* idle in flag */
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0, /* enable FCS */
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FCSP_ONES, /* FCS preset to all ones (V.41) */
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SYNC_AA, /* use AAh as sync char */
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0, /* disable pad characters */
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},
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0, 0, 0, 0, /* clear rfar1-4 */
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POLY_V41, /* use V.41 CRC polynomial */
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};
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static cx_opt_bisync_t opt_bisync_dflt = { /* default bisync options */
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{ /* cor1 */
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8-1, /* 8-bit char length */
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0, /* don't ignore parity */
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PARM_NOPAR, /* no parity */
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PAR_EVEN, /* even parity */
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},
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{ /* cor2 */
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3-2, /* send three SYN chars */
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CRC_DONT_INVERT,/* don't invert CRC (CRC-16) */
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0, /* use ASCII, not EBCDIC */
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0, /* disable bcc append */
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BCC_CRC16, /* user CRC16, not LRC */
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},
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{ /* cor3 */
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0, /* send 0 pad chars */
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IDLE_FLAG, /* idle in SYN */
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0, /* enable FCS */
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FCSP_ZEROS, /* FCS preset to all zeros (CRC-16) */
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PAD_AA, /* use AAh as pad char */
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0, /* disable pad characters */
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},
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{ /* cor6 */
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10, /* DLE - disable special termination char */
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},
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POLY_16, /* use CRC-16 polynomial */
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};
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static cx_opt_x21_t opt_x21_dflt = { /* default x21 options */
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{ /* cor1 */
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8-1, /* 8-bit char length */
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0, /* don't ignore parity */
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PARM_NOPAR, /* no parity */
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PAR_EVEN, /* even parity */
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},
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{ /* cor2 */
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0,
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0, /* disable embedded transmitter cmds */
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0,
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},
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{ /* cor3 */
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0,
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0, /* disable special character detect */
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0, /* don't treat SYN as special condition */
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0, /* disable steady state detect */
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X21SYN_2, /* 2 SYN chars on receive are required */
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},
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{ /* cor6 */
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16, /* SYN - standard SYN character */
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},
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0, 0, 0, /* clear schr1-3 */
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};
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static int cx_probe_chip (int base);
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static void cx_setup_chip (cx_chip_t *c);
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static void cx_init_board (cx_board_t *b, int num, int port, int irq, int dma,
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int chain, int rev, int osc, int rev2, int osc2);
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static void cx_reinit_board (cx_board_t *b);
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/*
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* Wait for CCR to clear.
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*/
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void cx_cmd (int base, int cmd)
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{
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unsigned short port = CCR(base);
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unsigned short count;
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/* Wait 10 msec for the previous command to complete. */
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for (count=0; inb(port) && count<20000; ++count)
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continue;
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/* Issue the command. */
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outb (port, cmd);
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/* Wait 10 msec for the command to complete. */
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for (count=0; inb(port) && count<20000; ++count)
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continue;
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}
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/*
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* Reset the chip.
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*/
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static int cx_reset (unsigned short port)
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{
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int count;
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/* Wait up to 10 msec for revision code to appear after reset. */
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for (count=0; count<20000; ++count)
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if (inb(GFRCR(port)) != 0)
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break;
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cx_cmd (port, CCR_RSTALL);
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/* Firmware revision code should clear imediately. */
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/* Wait up to 10 msec for revision code to appear again. */
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for (count=0; count<20000; ++count)
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if (inb(GFRCR(port)) != 0)
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return (1);
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/* Reset failed. */
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return (0);
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}
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/*
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* Check if the CD2400 board is present at the given base port.
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*/
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static int cx_probe_chained_board (int port, int *c0, int *c1)
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{
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int rev, i;
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/* Read and check the board revision code. */
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rev = inb (BSR(port));
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*c0 = *c1 = 0;
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switch (rev & BSR_VAR_MASK) {
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case CRONYX_100: *c0 = 1; break;
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case CRONYX_400: *c1 = 1; break;
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case CRONYX_500: *c0 = *c1 = 1; break;
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case CRONYX_410: *c0 = 1; break;
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case CRONYX_810: *c0 = *c1 = 1; break;
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case CRONYX_410s: *c0 = 1; break;
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case CRONYX_810s: *c0 = *c1 = 1; break;
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case CRONYX_440: *c0 = 1; break;
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case CRONYX_840: *c0 = *c1 = 1; break;
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case CRONYX_401: *c0 = 1; break;
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case CRONYX_801: *c0 = *c1 = 1; break;
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case CRONYX_401s: *c0 = 1; break;
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case CRONYX_801s: *c0 = *c1 = 1; break;
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case CRONYX_404: *c0 = 1; break;
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case CRONYX_703: *c0 = *c1 = 1; break;
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default: return (0); /* invalid variant code */
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}
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switch (rev & BSR_OSC_MASK) {
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case BSR_OSC_20: /* 20 MHz */
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case BSR_OSC_18432: /* 18.432 MHz */
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break;
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default:
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return (0); /* oscillator frequency does not match */
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}
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for (i=2; i<0x10; i+=2)
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if ((inb (BSR(port)+i) & BSR_REV_MASK) != (rev & BSR_REV_MASK))
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return (0); /* status changed? */
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return (1);
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}
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/*
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* Check if the CD2400 board is present at the given base port.
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*/
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int
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cx_probe_board (int port)
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{
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int c0, c1, c2=0, c3=0, result;
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if (! cx_probe_chained_board (port, &c0, &c1))
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return (0); /* no board detected */
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if (! (inb (BSR(port)) & BSR_NOCHAIN)) { /* chained board attached */
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if (! cx_probe_chained_board (port + 0x10, &c2, &c3))
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return (0); /* invalid chained board? */
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if (! (inb (BSR(port+0x10)) & BSR_NOCHAIN))
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return (0); /* invalid chained board flag? */
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}
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/* Turn off the reset bit. */
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outb (BCR0(port), BCR0_NORESET);
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if (c2 || c3)
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outb (BCR0(port + 0x10), BCR0_NORESET);
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result = 1;
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if (c0 && ! cx_probe_chip (CS0(port)))
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result = 0; /* no CD2400 chip here */
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else if (c1 && ! cx_probe_chip (CS1(port)))
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result = 0; /* no second CD2400 chip */
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else if (c2 && ! cx_probe_chip (CS0(port + 0x10)))
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result = 0; /* no CD2400 chip on the slave board */
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else if (c3 && ! cx_probe_chip (CS1(port + 0x10)))
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result = 0; /* no second CD2400 chip on the slave board */
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/* Reset the controller. */
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outb (BCR0(port), 0);
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if (c2 || c3)
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outb (BCR0(port + 0x10), 0);
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/* Yes, we really have valid CD2400 board. */
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return (result);
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}
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/*
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* Check if the CD2400 chip is present at the given base port.
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*/
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static int cx_probe_chip (int base)
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{
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int rev, newrev, count;
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/* Wait up to 10 msec for revision code to appear after reset. */
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for (count=0; inb(GFRCR(base))==0; ++count)
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if (count >= 20000)
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return (0); /* reset failed */
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/* Read and check the global firmware revision code. */
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rev = inb (GFRCR(base));
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if (rev<REVCL_MIN || rev>REVCL_MAX)
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return (0); /* CD2400 revision does not match */
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/* Reset the chip. */
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if (! cx_reset (base))
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return (0);
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/* Read and check the new global firmware revision code. */
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newrev = inb (GFRCR(base));
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if (newrev != rev)
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return (0); /* revision changed */
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/* Yes, we really have CD2400 chip here. */
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return (1);
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}
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/*
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* Probe and initialize the board structure.
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*/
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void cx_init (cx_board_t *b, int num, int port, int irq, int dma)
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{
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int rev, chain, rev2;
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rev = inb (BSR(port));
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chain = !(rev & BSR_NOCHAIN);
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rev2 = chain ? inb (BSR(port+0x10)) : 0;
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cx_init_board (b, num, port, irq, dma, chain,
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(rev & BSR_VAR_MASK), (rev & BSR_OSC_MASK),
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(rev2 & BSR_VAR_MASK), (rev2 & BSR_OSC_MASK));
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}
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/*
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* Initialize the board structure, given the type of the board.
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*/
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static void
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cx_init_board (cx_board_t *b, int num, int port, int irq, int dma,
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int chain, int rev, int osc, int rev2, int osc2)
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{
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cx_chan_t *c;
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int i, c0, c1;
|
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/* Initialize board structure. */
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b->port = port;
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b->num = num;
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b->irq = irq;
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b->dma = dma;
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b->if0type = b->if8type = cx_iftype;
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/* Set channels 0 and 8 mode, set DMA and IRQ. */
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b->bcr0 = b->bcr0b = BCR0_NORESET | dmamask[b->dma] | irqmask[b->irq];
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|
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/* Clear DTR[0..3] and DTR[8..12]. */
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b->bcr1 = b->bcr1b = 0;
|
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|
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/* Initialize chip structures. */
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for (i=0; i<NCHIP; ++i) {
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b->chip[i].num = i;
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b->chip[i].board = b;
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}
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b->chip[0].port = CS0(port);
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b->chip[1].port = CS1(port);
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b->chip[2].port = CS0(port+0x10);
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b->chip[3].port = CS1(port+0x10);
|
|
|
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/*------------------ Master board -------------------*/
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|
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/* Read and check the board revision code. */
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c0 = c1 = 0;
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b->name[0] = 0;
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switch (rev) {
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case CRONYX_100: strcpy (b->name, "100"); c0 = 1; break;
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case CRONYX_400: strcpy (b->name, "400"); c1 = 1; break;
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case CRONYX_500: strcpy (b->name, "500"); c0 = c1 = 1; break;
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case CRONYX_410: strcpy (b->name, "410"); c0 = 1; break;
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case CRONYX_810: strcpy (b->name, "810"); c0 = c1 = 1; break;
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case CRONYX_410s: strcpy (b->name, "410s"); c0 = 1; break;
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case CRONYX_810s: strcpy (b->name, "810s"); c0 = c1 = 1; break;
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case CRONYX_440: strcpy (b->name, "440"); c0 = 1; break;
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case CRONYX_840: strcpy (b->name, "840"); c0 = c1 = 1; break;
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case CRONYX_401: strcpy (b->name, "401"); c0 = 1; break;
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case CRONYX_801: strcpy (b->name, "801"); c0 = c1 = 1; break;
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case CRONYX_401s: strcpy (b->name, "401s"); c0 = 1; break;
|
|
case CRONYX_801s: strcpy (b->name, "801s"); c0 = c1 = 1; break;
|
|
case CRONYX_404: strcpy (b->name, "404"); c0 = 1; break;
|
|
case CRONYX_703: strcpy (b->name, "703"); c0 = c1 = 1; break;
|
|
}
|
|
|
|
switch (osc) {
|
|
default:
|
|
case BSR_OSC_20: /* 20 MHz */
|
|
b->chip[0].oscfreq = b->chip[1].oscfreq = 20000000L;
|
|
strcat (b->name, "a");
|
|
break;
|
|
case BSR_OSC_18432: /* 18.432 MHz */
|
|
b->chip[0].oscfreq = b->chip[1].oscfreq = 18432000L;
|
|
strcat (b->name, "b");
|
|
break;
|
|
}
|
|
|
|
if (! c0)
|
|
b->chip[0].port = 0;
|
|
if (! c1)
|
|
b->chip[1].port = 0;
|
|
|
|
/*------------------ Slave board -------------------*/
|
|
|
|
if (! chain) {
|
|
b->chip[2].oscfreq = b->chip[3].oscfreq = 0L;
|
|
b->chip[2].port = b->chip[3].port = 0;
|
|
} else {
|
|
/* Read and check the board revision code. */
|
|
c0 = c1 = 0;
|
|
strcat (b->name, "/");
|
|
switch (rev2) {
|
|
case CRONYX_100: strcat(b->name,"100"); c0=1; break;
|
|
case CRONYX_400: strcat(b->name,"400"); c1=1; break;
|
|
case CRONYX_500: strcat(b->name,"500"); c0=c1=1; break;
|
|
case CRONYX_410: strcat(b->name,"410"); c0=1; break;
|
|
case CRONYX_810: strcat(b->name,"810"); c0=c1=1; break;
|
|
case CRONYX_410s: strcat(b->name,"410s"); c0=1; break;
|
|
case CRONYX_810s: strcat(b->name,"810s"); c0=c1=1; break;
|
|
case CRONYX_440: strcat(b->name,"440"); c0=1; break;
|
|
case CRONYX_840: strcat(b->name,"840"); c0=c1=1; break;
|
|
case CRONYX_401: strcat(b->name,"401"); c0=1; break;
|
|
case CRONYX_801: strcat(b->name,"801"); c0=c1=1; break;
|
|
case CRONYX_401s: strcat(b->name,"401s"); c0=1; break;
|
|
case CRONYX_801s: strcat(b->name,"801s"); c0=c1=1; break;
|
|
case CRONYX_404: strcat(b->name,"404"); c0=1; break;
|
|
case CRONYX_703: strcat(b->name,"703"); c0=c1=1; break;
|
|
}
|
|
|
|
switch (osc2) {
|
|
default:
|
|
case BSR_OSC_20: /* 20 MHz */
|
|
b->chip[2].oscfreq = b->chip[3].oscfreq = 20000000L;
|
|
strcat (b->name, "a");
|
|
break;
|
|
case BSR_OSC_18432: /* 18.432 MHz */
|
|
b->chip[2].oscfreq = b->chip[3].oscfreq = 18432000L;
|
|
strcat (b->name, "b");
|
|
break;
|
|
}
|
|
|
|
if (! c0)
|
|
b->chip[2].port = 0;
|
|
if (! c1)
|
|
b->chip[3].port = 0;
|
|
}
|
|
|
|
/* Initialize channel structures. */
|
|
for (i=0; i<NCHAN; ++i) {
|
|
cx_chan_t *c = b->chan + i;
|
|
|
|
c->num = i;
|
|
c->board = b;
|
|
c->chip = b->chip + i*NCHIP/NCHAN;
|
|
c->stat = b->stat + i;
|
|
c->type = T_NONE;
|
|
}
|
|
|
|
/*------------------ Master board -------------------*/
|
|
|
|
switch (rev) {
|
|
case CRONYX_400:
|
|
break;
|
|
case CRONYX_100:
|
|
case CRONYX_500:
|
|
b->chan[0].type = T_UNIV_RS232;
|
|
break;
|
|
case CRONYX_410:
|
|
case CRONYX_810:
|
|
b->chan[0].type = T_UNIV_V35;
|
|
for (i=1; i<4; ++i)
|
|
b->chan[i].type = T_UNIV_RS232;
|
|
break;
|
|
case CRONYX_410s:
|
|
case CRONYX_810s:
|
|
b->chan[0].type = T_UNIV_V35;
|
|
for (i=1; i<4; ++i)
|
|
b->chan[i].type = T_SYNC_RS232;
|
|
break;
|
|
case CRONYX_440:
|
|
case CRONYX_840:
|
|
b->chan[0].type = T_UNIV_V35;
|
|
for (i=1; i<4; ++i)
|
|
b->chan[i].type = T_SYNC_V35;
|
|
break;
|
|
case CRONYX_401:
|
|
case CRONYX_801:
|
|
b->chan[0].type = T_UNIV_RS449;
|
|
for (i=1; i<4; ++i)
|
|
b->chan[i].type = T_UNIV_RS232;
|
|
break;
|
|
case CRONYX_401s:
|
|
case CRONYX_801s:
|
|
b->chan[0].type = T_UNIV_RS449;
|
|
for (i=1; i<4; ++i)
|
|
b->chan[i].type = T_SYNC_RS232;
|
|
break;
|
|
case CRONYX_404:
|
|
b->chan[0].type = T_UNIV_RS449;
|
|
for (i=1; i<4; ++i)
|
|
b->chan[i].type = T_SYNC_RS449;
|
|
break;
|
|
case CRONYX_703:
|
|
b->chan[0].type = T_UNIV_RS449;
|
|
for (i=1; i<3; ++i)
|
|
b->chan[i].type = T_SYNC_RS449;
|
|
break;
|
|
}
|
|
|
|
/* If the second controller is present,
|
|
* then we have 4..7 channels in async. mode */
|
|
if (b->chip[1].port)
|
|
for (i=4; i<8; ++i)
|
|
b->chan[i].type = T_UNIV_RS232;
|
|
|
|
/*------------------ Slave board -------------------*/
|
|
|
|
if (chain) {
|
|
switch (rev2) {
|
|
case CRONYX_400:
|
|
break;
|
|
case CRONYX_100:
|
|
case CRONYX_500:
|
|
b->chan[8].type = T_UNIV_RS232;
|
|
break;
|
|
case CRONYX_410:
|
|
case CRONYX_810:
|
|
b->chan[8].type = T_UNIV_V35;
|
|
for (i=9; i<12; ++i)
|
|
b->chan[i].type = T_UNIV_RS232;
|
|
break;
|
|
case CRONYX_410s:
|
|
case CRONYX_810s:
|
|
b->chan[8].type = T_UNIV_V35;
|
|
for (i=9; i<12; ++i)
|
|
b->chan[i].type = T_SYNC_RS232;
|
|
break;
|
|
case CRONYX_440:
|
|
case CRONYX_840:
|
|
b->chan[8].type = T_UNIV_V35;
|
|
for (i=9; i<12; ++i)
|
|
b->chan[i].type = T_SYNC_V35;
|
|
break;
|
|
case CRONYX_401:
|
|
case CRONYX_801:
|
|
b->chan[8].type = T_UNIV_RS449;
|
|
for (i=9; i<12; ++i)
|
|
b->chan[i].type = T_UNIV_RS232;
|
|
break;
|
|
case CRONYX_401s:
|
|
case CRONYX_801s:
|
|
b->chan[8].type = T_UNIV_RS449;
|
|
for (i=9; i<12; ++i)
|
|
b->chan[i].type = T_UNIV_RS232;
|
|
break;
|
|
case CRONYX_404:
|
|
b->chan[8].type = T_UNIV_RS449;
|
|
for (i=9; i<12; ++i)
|
|
b->chan[i].type = T_SYNC_RS449;
|
|
break;
|
|
case CRONYX_703:
|
|
b->chan[8].type = T_UNIV_RS449;
|
|
for (i=9; i<11; ++i)
|
|
b->chan[i].type = T_SYNC_RS449;
|
|
break;
|
|
}
|
|
|
|
/* If the second controller is present,
|
|
* then we have 4..7 channels in async. mode */
|
|
if (b->chip[3].port)
|
|
for (i=12; i<16; ++i)
|
|
b->chan[i].type = T_UNIV_RS232;
|
|
}
|
|
|
|
b->nuniv = b->nsync = b->nasync = 0;
|
|
for (c=b->chan; c<b->chan+NCHAN; ++c)
|
|
switch (c->type) {
|
|
case T_ASYNC: ++b->nasync; break;
|
|
case T_UNIV_RS232:
|
|
case T_UNIV_RS449:
|
|
case T_UNIV_V35: ++b->nuniv; break;
|
|
case T_SYNC_RS232:
|
|
case T_SYNC_V35:
|
|
case T_SYNC_RS449: ++b->nsync; break;
|
|
}
|
|
|
|
cx_reinit_board (b);
|
|
}
|
|
|
|
/*
|
|
* Reinitialize all channels, using new options and baud rate.
|
|
*/
|
|
static void
|
|
cx_reinit_board (cx_board_t *b)
|
|
{
|
|
cx_chan_t *c;
|
|
|
|
b->if0type = b->if8type = cx_iftype;
|
|
for (c=b->chan; c<b->chan+NCHAN; ++c) {
|
|
switch (c->type) {
|
|
default:
|
|
case T_NONE:
|
|
continue;
|
|
case T_UNIV_RS232:
|
|
case T_UNIV_RS449:
|
|
case T_UNIV_V35:
|
|
c->mode = (cx_univ_mode == M_ASYNC) ?
|
|
M_ASYNC : cx_sync_mode;
|
|
break;
|
|
case T_SYNC_RS232:
|
|
case T_SYNC_V35:
|
|
case T_SYNC_RS449:
|
|
c->mode = cx_sync_mode;
|
|
break;
|
|
case T_ASYNC:
|
|
c->mode = M_ASYNC;
|
|
break;
|
|
}
|
|
c->rxbaud = cx_rxbaud;
|
|
c->txbaud = cx_txbaud;
|
|
c->opt = chan_opt_dflt;
|
|
c->aopt = opt_async_dflt;
|
|
c->hopt = opt_hdlc_dflt;
|
|
c->bopt = opt_bisync_dflt;
|
|
c->xopt = opt_x21_dflt;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Set up the board.
|
|
*/
|
|
void cx_setup_board (cx_board_t *b)
|
|
{
|
|
int i;
|
|
|
|
/* Disable DMA channel. */
|
|
outb (DMA_MASK, (b->dma & 3) | DMA_MASK_CLEAR);
|
|
|
|
/* Reset the controller. */
|
|
outb (BCR0(b->port), 0);
|
|
if (b->chip[2].port || b->chip[3].port)
|
|
outb (BCR0(b->port+0x10), 0);
|
|
|
|
/*
|
|
* Set channels 0 and 8 to RS232 async. mode.
|
|
* Enable DMA and IRQ.
|
|
*/
|
|
outb (BCR0(b->port), b->bcr0);
|
|
if (b->chip[2].port || b->chip[3].port)
|
|
outb (BCR0(b->port+0x10), b->bcr0b);
|
|
|
|
/* Clear DTR[0..3] and DTR[8..12]. */
|
|
outw (BCR1(b->port), b->bcr1);
|
|
if (b->chip[2].port || b->chip[3].port)
|
|
outw (BCR1(b->port+0x10), b->bcr1b);
|
|
|
|
/* Initialize all controllers. */
|
|
for (i=0; i<NCHIP; ++i)
|
|
if (b->chip[i].port)
|
|
cx_setup_chip (b->chip + i);
|
|
|
|
/* Set up DMA channel to master mode. */
|
|
outb (DMA_MODE, (b->dma & 3) | DMA_MODE_MASTER);
|
|
|
|
/* Enable DMA channel. */
|
|
outb (DMA_MASK, b->dma & 3);
|
|
|
|
/* Initialize all channels. */
|
|
for (i=0; i<NCHAN; ++i)
|
|
if (b->chan[i].type != T_NONE)
|
|
cx_setup_chan (b->chan + i);
|
|
}
|
|
|
|
/*
|
|
* Initialize the board.
|
|
*/
|
|
static void cx_setup_chip (cx_chip_t *c)
|
|
{
|
|
/* Reset the chip. */
|
|
cx_reset (c->port);
|
|
|
|
/*
|
|
* Set all interrupt level registers to the same value.
|
|
* This enables the internal CD2400 priority scheme.
|
|
*/
|
|
outb (RPILR(c->port), BRD_INTR_LEVEL);
|
|
outb (TPILR(c->port), BRD_INTR_LEVEL);
|
|
outb (MPILR(c->port), BRD_INTR_LEVEL);
|
|
|
|
/* Set bus error count to zero. */
|
|
outb (BERCNT(c->port), 0);
|
|
|
|
/* Set 16-bit DMA mode. */
|
|
outb (DMR(c->port), 0);
|
|
|
|
/* Set timer period register to 1 msec (approximately). */
|
|
outb (TPR(c->port), 10);
|
|
}
|
|
|
|
/*
|
|
* Initialize the CD2400 channel.
|
|
*/
|
|
void cx_setup_chan (cx_chan_t *c)
|
|
{
|
|
unsigned short port = c->chip->port;
|
|
int clock, period;
|
|
|
|
if (c->num == 0) {
|
|
c->board->bcr0 &= ~BCR0_UMASK;
|
|
if (c->mode != M_ASYNC)
|
|
c->board->bcr0 |= BCR0_UM_SYNC;
|
|
if (c->board->if0type &&
|
|
(c->type==T_UNIV_RS449 || c->type==T_UNIV_V35))
|
|
c->board->bcr0 |= BCR0_UI_RS449;
|
|
outb (BCR0(c->board->port), c->board->bcr0);
|
|
} else if (c->num == 8) {
|
|
c->board->bcr0b &= ~BCR0_UMASK;
|
|
if (c->mode != M_ASYNC)
|
|
c->board->bcr0b |= BCR0_UM_SYNC;
|
|
if (c->board->if8type &&
|
|
(c->type==T_UNIV_RS449 || c->type==T_UNIV_V35))
|
|
c->board->bcr0b |= BCR0_UI_RS449;
|
|
outb (BCR0(c->board->port+0x10), c->board->bcr0b);
|
|
}
|
|
|
|
/* set current channel number */
|
|
outb (CAR(port), c->num & 3);
|
|
|
|
/* reset the channel */
|
|
cx_cmd (port, CCR_CLRCH);
|
|
|
|
/* set LIVR to contain the board and channel numbers */
|
|
outb (LIVR(port), c->board->num << 6 | c->num << 2);
|
|
|
|
/* clear DTR, RTS, set TXCout/DTR pin */
|
|
outb (MSVR_RTS(port), 0);
|
|
outb (MSVR_DTR(port), c->mode==M_ASYNC ? 0 : MSV_TXCOUT);
|
|
|
|
switch (c->mode) { /* initialize the channel mode */
|
|
case M_ASYNC:
|
|
/* set receiver timeout register */
|
|
outw (RTPR(port), 10); /* 10 msec, see TPR */
|
|
|
|
outb (CMR(port), CMR_RXDMA | CMR_TXDMA | CMR_ASYNC);
|
|
outb (COR1(port), BYTE c->aopt.cor1);
|
|
outb (COR2(port), BYTE c->aopt.cor2);
|
|
outb (COR3(port), BYTE c->aopt.cor3);
|
|
outb (COR6(port), BYTE c->aopt.cor6);
|
|
outb (COR7(port), BYTE c->aopt.cor7);
|
|
outb (SCHR1(port), c->aopt.schr1);
|
|
outb (SCHR2(port), c->aopt.schr2);
|
|
outb (SCHR3(port), c->aopt.schr3);
|
|
outb (SCHR4(port), c->aopt.schr4);
|
|
outb (SCRL(port), c->aopt.scrl);
|
|
outb (SCRH(port), c->aopt.scrh);
|
|
outb (LNXT(port), c->aopt.lnxt);
|
|
break;
|
|
case M_HDLC:
|
|
outb (CMR(port), CMR_RXDMA | CMR_TXDMA | CMR_HDLC);
|
|
outb (COR1(port), BYTE c->hopt.cor1);
|
|
outb (COR2(port), BYTE c->hopt.cor2);
|
|
outb (COR3(port), BYTE c->hopt.cor3);
|
|
outb (RFAR1(port), c->hopt.rfar1);
|
|
outb (RFAR2(port), c->hopt.rfar2);
|
|
outb (RFAR3(port), c->hopt.rfar3);
|
|
outb (RFAR4(port), c->hopt.rfar4);
|
|
outb (CPSR(port), c->hopt.cpsr);
|
|
break;
|
|
case M_BISYNC:
|
|
outb (CMR(port), CMR_RXDMA | CMR_TXDMA | CMR_BISYNC);
|
|
outb (COR1(port), BYTE c->bopt.cor1);
|
|
outb (COR2(port), BYTE c->bopt.cor2);
|
|
outb (COR3(port), BYTE c->bopt.cor3);
|
|
outb (COR6(port), BYTE c->bopt.cor6);
|
|
outb (CPSR(port), c->bopt.cpsr);
|
|
break;
|
|
case M_X21:
|
|
outb (CMR(port), CMR_RXDMA | CMR_TXDMA | CMR_X21);
|
|
outb (COR1(port), BYTE c->xopt.cor1);
|
|
outb (COR2(port), BYTE c->xopt.cor2);
|
|
outb (COR3(port), BYTE c->xopt.cor3);
|
|
outb (COR6(port), BYTE c->xopt.cor6);
|
|
outb (SCHR1(port), c->xopt.schr1);
|
|
outb (SCHR2(port), c->xopt.schr2);
|
|
outb (SCHR3(port), c->xopt.schr3);
|
|
break;
|
|
}
|
|
|
|
/* set mode-independent options */
|
|
outb (COR4(port), BYTE c->opt.cor4);
|
|
outb (COR5(port), BYTE c->opt.cor5);
|
|
|
|
/* set up receiver clock values */
|
|
if (c->mode == M_ASYNC || c->opt.rcor.dpll) {
|
|
cx_clock (c->chip->oscfreq, c->rxbaud, &clock, &period);
|
|
c->opt.rcor.clk = clock;
|
|
} else {
|
|
c->opt.rcor.clk = CLK_EXT;
|
|
period = 1;
|
|
}
|
|
outb (RCOR(port), BYTE c->opt.rcor);
|
|
outb (RBPR(port), period);
|
|
|
|
/* set up transmitter clock values */
|
|
if (c->mode == M_ASYNC || !c->opt.tcor.ext1x) {
|
|
unsigned ext1x = c->opt.tcor.ext1x;
|
|
c->opt.tcor.ext1x = 0;
|
|
cx_clock (c->chip->oscfreq, c->txbaud, &clock, &period);
|
|
c->opt.tcor.clk = clock;
|
|
c->opt.tcor.ext1x = ext1x;
|
|
} else {
|
|
c->opt.tcor.clk = CLK_EXT;
|
|
period = 1;
|
|
}
|
|
outb (TCOR(port), BYTE c->opt.tcor);
|
|
outb (TBPR(port), period);
|
|
|
|
/* set receiver A buffer physical address */
|
|
c->arphys = vtophys (c->arbuf);
|
|
outw (ARBADRU(port), (unsigned short) (c->arphys>>16));
|
|
outw (ARBADRL(port), (unsigned short) c->arphys);
|
|
|
|
/* set receiver B buffer physical address */
|
|
c->brphys = vtophys (c->brbuf);
|
|
outw (BRBADRU(port), (unsigned short) (c->brphys>>16));
|
|
outw (BRBADRL(port), (unsigned short) c->brphys);
|
|
|
|
/* set transmitter A buffer physical address */
|
|
c->atphys = vtophys (c->atbuf);
|
|
outw (ATBADRU(port), (unsigned short) (c->atphys>>16));
|
|
outw (ATBADRL(port), (unsigned short) c->atphys);
|
|
|
|
/* set transmitter B buffer physical address */
|
|
c->btphys = vtophys (c->btbuf);
|
|
outw (BTBADRU(port), (unsigned short) (c->btphys>>16));
|
|
outw (BTBADRL(port), (unsigned short) c->btphys);
|
|
|
|
c->dtr = 0;
|
|
c->rts = 0;
|
|
}
|
|
|
|
/*
|
|
* Control DTR signal for the channel.
|
|
* Turn it on/off.
|
|
*/
|
|
void cx_chan_dtr (cx_chan_t *c, int on)
|
|
{
|
|
c->dtr = on ? 1 : 0;
|
|
|
|
if (c->mode == M_ASYNC) {
|
|
outb (CAR(c->chip->port), c->num & 3);
|
|
outb (MSVR_DTR(c->chip->port), on ? MSV_DTR : 0);
|
|
return;
|
|
}
|
|
|
|
switch (c->num) {
|
|
default:
|
|
/* Channels 4..7 and 12..15 in syncronous mode
|
|
* have no DTR signal. */
|
|
break;
|
|
|
|
case 1: case 2: case 3:
|
|
if (c->type == T_UNIV_RS232)
|
|
break;
|
|
case 0:
|
|
if (on)
|
|
c->board->bcr1 |= 0x100 << c->num;
|
|
else
|
|
c->board->bcr1 &= ~(0x100 << c->num);
|
|
outw (BCR1(c->board->port), c->board->bcr1);
|
|
break;
|
|
|
|
case 9: case 10: case 11:
|
|
if (c->type == T_UNIV_RS232)
|
|
break;
|
|
case 8:
|
|
if (on)
|
|
c->board->bcr1b |= 0x100 << (c->num & 3);
|
|
else
|
|
c->board->bcr1b &= ~(0x100 << (c->num & 3));
|
|
outw (BCR1(c->board->port+0x10), c->board->bcr1b);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Control RTS signal for the channel.
|
|
* Turn it on/off.
|
|
*/
|
|
void
|
|
cx_chan_rts (cx_chan_t *c, int on)
|
|
{
|
|
c->rts = on ? 1 : 0;
|
|
outb (CAR(c->chip->port), c->num & 3);
|
|
outb (MSVR_RTS(c->chip->port), on ? MSV_RTS : 0);
|
|
}
|
|
|
|
|
|
/*
|
|
* Get the state of CARRIER signal of the channel.
|
|
*/
|
|
int
|
|
cx_chan_cd (cx_chan_t *c)
|
|
{
|
|
unsigned char sigval;
|
|
|
|
if (c->mode == M_ASYNC) {
|
|
outb (CAR(c->chip->port), c->num & 3);
|
|
return (inb (MSVR(c->chip->port)) & MSV_CD ? 1 : 0);
|
|
}
|
|
|
|
/*
|
|
* Channels 4..7 and 12..15 don't have CD signal available.
|
|
*/
|
|
switch (c->num) {
|
|
default:
|
|
return (1);
|
|
|
|
case 1: case 2: case 3:
|
|
if (c->type == T_UNIV_RS232)
|
|
return (1);
|
|
case 0:
|
|
sigval = inw (BSR(c->board->port)) >> 8;
|
|
break;
|
|
|
|
case 9: case 10: case 11:
|
|
if (c->type == T_UNIV_RS232)
|
|
return (1);
|
|
case 8:
|
|
sigval = inw (BSR(c->board->port+0x10)) >> 8;
|
|
break;
|
|
}
|
|
return (~sigval >> 4 >> (c->num & 3) & 1);
|
|
}
|
|
|
|
/*
|
|
* Compute CD2400 clock values.
|
|
*/
|
|
void cx_clock (long hz, long ba, int *clk, int *div)
|
|
{
|
|
static short clocktab[] = { 8, 32, 128, 512, 2048, 0 };
|
|
|
|
for (*clk=0; clocktab[*clk]; ++*clk) {
|
|
long c = ba * clocktab[*clk];
|
|
if (hz <= c*256) {
|
|
*div = (2 * hz + c) / (2 * c) - 1;
|
|
return;
|
|
}
|
|
}
|
|
/* Incorrect baud rate. Return some meaningful values. */
|
|
*clk = 0;
|
|
*div = 255;
|
|
}
|