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ca83142fc3
fact that access to RR0 does not need a prior write to the register index because the index always reverts to 0 after the indexed register has been accessed. Typically when a RR or WR is to accessed, one programs the index (which is a write to the control register), followed by a read or write to the actual indexed register (a read pr write to the same control register). When this non-atomic sequence is interrupted after having written the index and low-level console I/O is done in that situation, the write to program the index will actually write to the indexed register and nuke state. This almost always yields a wedge. By not programming the index register and instead just reading from RR0, the worst case scenario is non-fatal. For if we don't actually read from RR0 but some other register we get an invalid status, which may lead us to conclude that the transit data register is empty when it's not or that the receive data register contains data when it doesn't. Hence, we may lose an output character or get a sporadic input character, but given the situation this is a non-issue. Full serialization is not possible due to the fact that this code needs to work from DDB and before mutex initialization has happened. In collaboration with: kris@, marius@ Tested by: kris@ MFC after: 1 day X-MFC: 5.4-RELEASE candidate |
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| .. | ||
| uart_bus_acpi.c | ||
| uart_bus_ebus.c | ||
| uart_bus_isa.c | ||
| uart_bus_pccard.c | ||
| uart_bus_pci.c | ||
| uart_bus_puc.c | ||
| uart_bus.h | ||
| uart_core.c | ||
| uart_cpu_alpha.c | ||
| uart_cpu_amd64.c | ||
| uart_cpu_i386.c | ||
| uart_cpu_ia64.c | ||
| uart_cpu_pc98.c | ||
| uart_cpu_sparc64.c | ||
| uart_cpu.h | ||
| uart_dbg.c | ||
| uart_dev_ns8250.c | ||
| uart_dev_sab82532.c | ||
| uart_dev_z8530.c | ||
| uart_if.m | ||
| uart_kbd_sun_tables.h | ||
| uart_kbd_sun.c | ||
| uart_kbd_sun.h | ||
| uart_subr.c | ||
| uart_tty.c | ||
| uart.h | ||