John Baldwin 92597e064b On some Intel CPUs with a P-state but not C-state invariant TSC the TSC ... may also halt in C2 and not just C3 (it seems that in some cases the BIOS advertises its C3 state as a C2 state in _CST). Just play it safe and disable both C2 and C3 states if a user forces the use of the TSC as the timecounter on such CPUs. PR: 192316 Differential Revision: https://reviews.freebsd.org/D1441 No objection from: jkim MFC after: 1 week		2015-01-05 20:44:44 +00:00
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acpica	don't set CR4 PSE bit on amd64	2014-07-23 15:53:29 +00:00
amd64	On some Intel CPUs with a P-state but not C-state invariant TSC the TSC	2015-01-05 20:44:44 +00:00
conf	Fix a missed comment from r276526.	2015-01-02 15:46:54 +00:00
ia32	Change the way the lcall $7,$0 is reflected to usermode. Instead of	2014-12-27 23:19:08 +00:00
include	For /dev/mem and /dev/kmem accesses, avoid asserting that addresses	2015-01-03 01:28:58 +00:00
linux32	Regen after r276508, r276509.	2015-01-01 18:43:31 +00:00
pci	Pull in r267961 and r267973 again. Fix for issues reported will follow.	2014-06-28 03:56:17 +00:00
vmm	Initialize all fields of 'struct vm_exception exception' before passing it to	2014-12-30 23:38:31 +00:00
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