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fd67ff5c7a
We have been incorrectly choosing the "hlt" idle method on modern AMD EPYC servers for C1 idle. This is because AMD also uses the Functional Fixed Hardware interface. Due to not parsing the table properly for AMD, and due to a weird quirk where the mwait latency for C1 is mis-interpreted as the latency for hlt, we wind up choosing hlt for c1, which has a far higher wake up latency (similar to IO) of roughly 400us on my test system (AMD 7502P). This patch fixes this by: - Looking for AMD in addition to Intel in the FFH (Note the vendor id of "2" for AMD is not publically documented, but AMD has confirmed they are using "2" and has promised to document it.) - Using mwait on AMD when specified in the table, and when CPUid says its supported - Fixing a weird issue where we copy the contents of cx_ptr for C1 and when moving to C2, we do not reinitialize cx_ptr. This leads to mwait being selected, and ignoring the specified i/o halt method unless we clear mwait before looking at the table for C2. Differential Revision: https://reviews.freebsd.org/D47444 Reviewed by: dab, kib, vangyzen Sponsored by: Netflix |
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xen | ||
_align.h | ||
_inttypes.h | ||
_limits.h | ||
_stdint.h | ||
_types.h | ||
acpica_machdep.h | ||
apicreg.h | ||
apicvar.h | ||
apm_bios.h | ||
bus_dma.h | ||
bus.h | ||
busdma_impl.h | ||
clock.h | ||
cputypes.h | ||
dump.h | ||
elf.h | ||
endian.h | ||
fdt.h | ||
float.h | ||
fpu.h | ||
frame.h | ||
ifunc.h | ||
init.h | ||
intr_machdep.h | ||
iommu.h | ||
kvm.h | ||
legacyvar.h | ||
mca.h | ||
metadata.h | ||
mptable.h | ||
ofw_machdep.h | ||
pci_cfgreg.h | ||
ppireg.h | ||
procctl.h | ||
psl.h | ||
ptrace.h | ||
pvclock.h | ||
reg.h | ||
segments.h | ||
setjmp.h | ||
sigframe.h | ||
signal.h | ||
specialreg.h | ||
stack.h | ||
stdarg.h | ||
sysarch.h | ||
timerreg.h | ||
tls.h | ||
trap.h | ||
ucode.h | ||
ucontext.h | ||
vdso.h | ||
vmware_guestrpc.h | ||
vmware.h | ||
x86_ieeefp.h | ||
x86_smp.h | ||
x86_var.h |