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27d5dc189c
It improves on sio(4) in the following areas: o Fully newbusified to allow for memory mapped I/O. This is a must for ia64 and sparc64, o Machine dependent code to take full advantage of machine and firm- ware specific ways to define serial consoles and/or debug ports. o Hardware abstraction layer to allow the driver to be used with various UARTs, such as the well-known ns8250 family of UARTs, the Siemens sab82532 or the Zilog Z8530. This is especially important for pc98 and sparc64 where it's common to have different UARTs, o The notion of system devices to unkludge low-level consoles and remote gdb ports and provides the mechanics necessary to support the keyboard on sparc64 (which is UART based). o The notion of a kernel interface so that a UART can be tied to something other than the well-known TTY interface. This is needed on sparc64 to present the user with a device and ioctl handling suitable for a keyboard, but also allows us to cleanly hide an UART when used as a debug port. Following is a list of features and bugs/flaws specific to the ns8250 family of UARTs as compared to their support in sio(4): o The uart(4) driver determines the FIFO size and automaticly takes advantages of larger FIFOs and/or additional features. Note that since I don't have sufficient access to 16[679]5x UARTs, hardware flow control has not been enabled. This is almost trivial to do, provided one can test. The downside of this is that broken UARTs are more likely to not work correctly with uart(4). The need for tunables or knobs may be large enough to warrant their creation. o The uart(4) driver does not share the same bumpy history as sio(4) and will therefore not provide the necessary hooks, tweaks, quirks or work-arounds to deal with once common hardware. To that extend, uart(4) supports a subset of the UARTs that sio(4) supports. The question before us is whether the subset is sufficient for current hardware. o There is no support for multiport UARTs in uart(4). The decision behind this is that uart(4) deals with one EIA RS232-C interface. Packaging of multiple interfaces in a single chip or on a single expansion board is beyond the scope of uart(4) and is now mostly left for puc(4) to deal with. Lack of hardware made it impossible to actually implement such a dependency other than is present for the dual channel SAB82532 and Z8350 SCCs. The current list of missing features is: o No configuration capabilities. A set of tunables and sysctls is being worked out. There are likely not going to be any or much compile-time knobs. Such configuration does not fit well with current hardware. o No support for the PPS API. This is partly dependent on the ability to configure uart(4) and partly dependent on having sufficient information to implement it properly. As usual, the manpage is present but lacks the attention the software has gotten.
253 lines
10 KiB
C
253 lines
10 KiB
C
/*
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* Copyright (c) 2003 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_UART_DEV_Z8530_H_
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#define _DEV_UART_DEV_Z8530_H_
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/*
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* Channel B control: 0
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* Channel B data: 1
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* Channel A control: 2
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* Channel A data: 3
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*
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* We expect a seperate subregion for each channel.
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*/
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#define REG_CTRL 0
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#define REG_DATA 1
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/* Write registers. */
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#define WR_CR 0 /* Command Register. */
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#define WR_IDT 1 /* Interrupt and Data Transfer Mode. */
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#define WR_IV 2 /* Interrupt Vector (shared). */
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#define WR_RPC 3 /* Receive Parameters and Control. */
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#define WR_MPM 4 /* Miscellaneous Parameters and Modes. */
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#define WR_TPC 5 /* Transmit Parameters and Control. */
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#define WR_SCAF 6 /* Sync Character or (SDLC) Address Field. */
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#define WR_SCF 7 /* Sync Character or (SDCL) Flag. */
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#define WR_EFC 7 /* Extended Feature and FIFO Control. */
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#define WR_TB 8 /* Transmit Buffer. */
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#define WR_MIC 9 /* Master Interrupt Control (shared). */
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#define WR_MCB1 10 /* Miscellaneous Control Bits (part 1 :-). */
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#define WR_CMC 11 /* Clock Mode Control. */
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#define WR_TCL 12 /* BRG Time Constant Low. */
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#define WR_TCH 13 /* BRG Time Constant High. */
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#define WR_MCB2 14 /* Miscellaneous Control Bits (part 2 :-). */
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#define WR_IC 15 /* Interrupt Control. */
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/* Read registers. */
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#define RR_BES 0 /* Buffer and External Status. */
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#define RR_SRC 1 /* Special Receive Condition. */
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#define RR_IV 2 /* Interrupt Vector. */
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#define RR_IP 3 /* Interrupt Pending (ch A only). */
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#define RR_MPM 4 /* Miscellaneous Parameters and Modes. */
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#define RR_TPC 5 /* Transmit Parameters and Control. */
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#define RR_BCL 6 /* Byte Count Low. */
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#define RR_BCH 7 /* Byte Count High. */
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#define RR_RB 8 /* Receive Buffer. */
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#define RR_RPC 9 /* Receive Parameters and Contro. */
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#define RR_MSB 10 /* Miscellaneous Status Bits. */
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#define RR_MCB1 11 /* Miscellaneous Control Bits (part 1). */
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#define RR_TCL 12 /* BRG Time Constant Low. */
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#define RR_TCH 13 /* BRG Time Constant High. */
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#define RR_EFC 14 /* Extended Feature and FIFO Control. */
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#define RR_IC 15 /* Interrupt Control. */
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/* Buffer and External Status (RR0). */
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#define BES_BRK 0x80 /* Break (Abort). */
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#define BES_TXU 0x40 /* Tx Underrun (EOM). */
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#define BES_CTS 0x20 /* CTS. */
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#define BES_SYNC 0x10 /* Sync. */
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#define BES_DCD 0x08 /* DCD. */
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#define BES_TXE 0x04 /* Tx Empty. */
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#define BES_ZC 0x02 /* Zero Count. */
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#define BES_RXA 0x01 /* Rx Available. */
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/* Clock Mode Control (WR11). */
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#define CMC_XTAL 0x80 /* -RTxC connects to quartz crystal. */
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#define CMC_RC_DPLL 0x60 /* Rx Clock from DPLL. */
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#define CMC_RC_BRG 0x40 /* Rx Clock from BRG. */
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#define CMC_RC_TRXC 0x20 /* Rx Clock from -TRxC. */
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#define CMC_RC_RTXC 0x00 /* Rx Clock from -RTxC. */
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#define CMC_TC_DPLL 0x18 /* Tx Clock from DPLL */
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#define CMC_TC_BRG 0x10 /* Tx Clock from BRG */
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#define CMC_TC_TRXC 0x08 /* Tx Clock from -TRxC. */
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#define CMC_TC_RTXC 0x00 /* Tx Clock from -RTxC. */
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#define CMC_TRXC_OUT 0x04 /* -TRxC is output. */
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#define CMC_TRXC_DPLL 0x03 /* -TRxC from DPLL */
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#define CMC_TRXC_BRG 0x02 /* -TRxC from BRG */
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#define CMC_TRXC_XMIT 0x01 /* -TRxC from Tx clock. */
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#define CMC_TRXC_XTAL 0x00 /* -TRxC from XTAL. */
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/* Command Register (WR0). */
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#define CR_RSTTXU 0xc0 /* Reset Tx. Underrun/EOM. */
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#define CR_RSTTXCRC 0x80 /* Reset Tx. CRC. */
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#define CR_RSTRXCRC 0x40 /* Reset Rx. CRC. */
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#define CR_RSTIUS 0x38 /* Reset Int. Under Service. */
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#define CR_RSTERR 0x30 /* Error Reset. */
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#define CR_RSTTXI 0x28 /* Reset Tx. Int. */
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#define CR_ENARXI 0x20 /* Enable Rx. Int. */
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#define CR_ABORT 0x18 /* Send Abort. */
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#define CR_RSTXSI 0x10 /* Reset Ext/Status Int. */
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/* Extended Feature and FIFO Control (WR7 prime). */
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#define EFC_ERE 0x40 /* Extended Read Enable. */
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#define EFC_FE 0x20 /* Transmit FIFO Empty. */
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#define EFC_RQT 0x10 /* Request Timing. */
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#define EFC_FHF 0x08 /* Receive FIFO Half Full. */
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#define EFC_RTS 0x04 /* Auto RTS Deactivation. */
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#define EFC_EOM 0x02 /* Auto EOM Reset. */
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#define EFC_FLAG 0x01 /* Auto SDLC Flag on Tx. */
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/* Interrupt Control (WR15). */
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#define IC_BRK 0x80 /* Break (Abort) IE. */
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#define IC_TXU 0x40 /* Tx Underrun IE. */
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#define IC_CTS 0x20 /* CTS IE. */
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#define IC_SYNC 0x10 /* Sync IE. */
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#define IC_DCD 0x08 /* DCD IE. */
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#define IC_FIFO 0x04 /* SDLC FIFO Enable. */
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#define IC_ZC 0x02 /* Zero Count IE. */
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#define IC_EF 0x01 /* Extended Feature Enable. */
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/* Interrupt and Data Transfer Mode (WR1). */
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#define IDT_WRE 0x80 /* Wait/DMA Request Enable. */
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#define IDT_REQ 0x40 /* DMA Request. */
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#define IDT_WRR 0x20 /* Wait/DMA Reuest on Receive. */
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#define IDT_RISC 0x18 /* Rx Int. on Special Condition Only. */
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#define IDT_RIA 0x10 /* Rx Int. on All Characters. */
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#define IDT_RIF 0x08 /* Rx Int. on First Character. */
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#define IDT_PSC 0x04 /* Parity is Special Condition. */
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#define IDT_TIE 0x02 /* Tx Int. Enable. */
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#define IDT_XIE 0x01 /* Ext. Int. Enable. */
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/* Interrupt Pending (RR3). */
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#define IP_RIA 0x20 /* Rx. Int. ch. A. */
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#define IP_TIA 0x10 /* Tx. Int. ch. A. */
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#define IP_SIA 0x08 /* Ext/Status Int. ch. A. */
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#define IP_RIB 0x04 /* Rx. Int. ch. B. */
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#define IP_TIB 0x02 /* Tx. Int. ch. B. */
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#define IP_SIB 0x01 /* Ext/Status Int. ch. B. */
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/* Interrupt Vector Status Low (RR2). */
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#define IV_SCA 0x0e /* Special Condition ch. A. */
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#define IV_RAA 0x0c /* Receive Available ch. A. */
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#define IV_XSA 0x0a /* External/Status Change ch. A. */
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#define IV_TEA 0x08 /* Transmitter Empty ch. A. */
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#define IV_SCB 0x06 /* Special Condition ch. B. */
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#define IV_RAB 0x04 /* Receive Available ch. B. */
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#define IV_XSB 0x02 /* External/Status Change ch. B. */
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#define IV_TEB 0x00 /* Transmitter Empty ch. B. */
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/* Miscellaneous Control Bits part 1 (WR10). */
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#define MCB1_CRC1 0x80 /* CRC presets to 1. */
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#define MCB1_FM0 0x60 /* FM0 Encoding. */
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#define MCB1_FM1 0x40 /* FM1 Encoding. */
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#define MCB1_NRZI 0x20 /* NRZI Encoding. */
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#define MCB1_NRZ 0x00 /* NRZ Encoding. */
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#define MCB1_AOP 0x10 /* Active On Poll. */
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#define MCB1_MI 0x08 /* Mark Idle. */
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#define MCB1_AOU 0x04 /* Abort On Underrun. */
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#define MCB1_LM 0x02 /* Loop Mode. */
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#define MCB1_SIX 0x01 /* 6 or 12 bit SYNC. */
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/* Miscellaneous Control Bits part 2 (WR14). */
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#define MCB2_NRZI 0xe0 /* DPLL - NRZI mode. */
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#define MCB2_FM 0xc0 /* DPLL - FM mode. */
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#define MCB2_RTXC 0xa0 /* DPLL - Clock from -RTxC. */
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#define MCB2_BRG 0x80 /* DPLL - Clock from BRG. */
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#define MCB2_OFF 0x60 /* DPLL - Disable. */
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#define MCB2_RMC 0x40 /* DPLL - Reset Missing Clock. */
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#define MCB2_ESM 0x20 /* DPLL - Enter Search Mode. */
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#define MCB2_LL 0x10 /* Local Loopback. */
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#define MCB2_AE 0x08 /* Auto Echo. */
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#define MCB2_REQ 0x04 /* Request Function. */
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#define MCB2_PCLK 0x02 /* BRG source is PCLK. */
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#define MCB2_BRGE 0x01 /* BRG enable. */
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/* Master Interrupt Control (WR9). */
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#define MIC_FHR 0xc0 /* Force Hardware Reset. */
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#define MIC_CRA 0x80 /* Channel Reset A. */
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#define MIC_CRB 0x40 /* Channel Reset B. */
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#define MIC_SIE 0x20 /* Software INTACK Enable. */
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#define MIC_SH 0x10 /* Status High. */
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#define MIC_MIE 0x08 /* Master Interrupt Enable. */
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#define MIC_DLC 0x04 /* Disable Lower Chain. */
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#define MIC_NV 0x02 /* No Vector. */
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#define MIC_VIS 0x01 /* Vector Includes Status. */
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/* Transmit/Receive Miscellaneous Parameters and Modes (WR4). */
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#define MPM_CM64 0xc0 /* X64 Clock Mode. */
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#define MPM_CM32 0x80 /* X32 Clock Mode. */
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#define MPM_CM16 0x40 /* X16 Clock Mode. */
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#define MPM_CM1 0x00 /* X1 Clock Mode. */
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#define MPM_EXT 0x30 /* External Sync Mode. */
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#define MPM_SDLC 0x20 /* SDLC mode. */
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#define MPM_BI 0x10 /* 16-bit Sync (bi-sync). */
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#define MPM_MONO 0x00 /* 8-bit Sync (mono-sync). */
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#define MPM_SB2 0x0c /* Async mode: 2 stopbits. */
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#define MPM_SB15 0x08 /* Async mode: 1.5 stopbits. */
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#define MPM_SB1 0x04 /* Async mode: 1 stopbit. */
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#define MPM_SYNC 0x00 /* Sync Mode Enable. */
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#define MPM_EVEN 0x02 /* Async mode: even parity. */
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#define MPM_PE 0x01 /* Async mode: parity enable. */
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/* Receive Parameters and Control (WR3). */
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#define RPC_RB8 0xc0 /* 8 databits. */
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#define RPC_RB6 0x80 /* 6 databits. */
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#define RPC_RB7 0x40 /* 7 databits. */
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#define RPC_RB5 0x00 /* 5 databits. */
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#define RPC_AE 0x20 /* Auto Enable. */
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#define RPC_EHM 0x10 /* Enter Hunt Mode. */
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#define RPC_CRC 0x08 /* CRC Enable. */
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#define RPC_ASM 0x04 /* Address Search Mode. */
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#define RPC_LI 0x02 /* SYNC Character Load Inhibit */
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#define RPC_RXE 0x01 /* Receiver Enable */
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/* Special Receive Condition (RR1). */
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#define SRC_EOF 0x80 /* End Of Frame. */
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#define SRC_FE 0x40 /* Framing Error. */
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#define SRC_OVR 0x20 /* Rx. Overrun. */
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#define SRC_PE 0x10 /* Parity Error. */
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#define SRC_RC0 0x08 /* Residue Code 0. */
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#define SRC_RC1 0x04 /* Residue Code 1. */
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#define SRC_RC2 0x02 /* Residue Code 2. */
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#define SRC_AS 0x01 /* All Sent. */
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/* Transmit Parameter and Control (WR5). */
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#define TPC_DTR 0x80 /* DTR. */
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#define TPC_TB8 0x60 /* 8 databits. */
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#define TPC_TB6 0x40 /* 6 databits. */
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#define TPC_TB7 0x20 /* 7 databits. */
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#define TPC_TB5 0x00 /* 5 or fewer databits. */
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#define TPC_BRK 0x10 /* Send break. */
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#define TPC_TXE 0x08 /* Transmitter Enable. */
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#define TPC_CRC16 0x04 /* CRC16. */
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#define TPC_RTS 0x02 /* RTS. */
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#define TPC_CRC 0x01 /* CRC Enable. */
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#endif /* _DEV_UART_DEV_Z8530_H_ */
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