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281 lines
11 KiB
C
281 lines
11 KiB
C
/*-
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* Copyright (c) 1998,1999,2000,2001 Søren Schmidt <sos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* ATA register defines */
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#define ATA_DATA 0x00 /* data register */
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#define ATA_ERROR 0x01 /* (R) error register */
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#define ATA_E_NM 0x02 /* no media */
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#define ATA_E_ABORT 0x04 /* command aborted */
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#define ATA_E_MCR 0x08 /* media change request */
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#define ATA_E_IDNF 0x10 /* ID not found */
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#define ATA_E_MC 0x20 /* media changed */
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#define ATA_E_UNC 0x40 /* uncorrectable data */
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#define ATA_E_ICRC 0x80 /* UDMA crc error */
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#define ATA_FEATURE 0x01 /* (W) feature register */
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#define ATA_F_DMA 0x01 /* enable DMA */
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#define ATA_F_OVL 0x02 /* enable overlap */
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#define ATA_COUNT 0x02 /* (W) sector count */
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#define ATA_IREASON 0x02 /* (R) interrupt reason */
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#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
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#define ATA_I_IN 0x02 /* read (1) | write (0) */
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#define ATA_I_RELEASE 0x04 /* released bus (1) */
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#define ATA_I_TAGMASK 0xf8 /* tag mask */
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#define ATA_SECTOR 0x03 /* sector # */
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#define ATA_CYL_LSB 0x04 /* cylinder# LSB */
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#define ATA_CYL_MSB 0x05 /* cylinder# MSB */
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#define ATA_DRIVE 0x06 /* Sector/Drive/Head register */
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#define ATA_D_LBA 0x40 /* use LBA addressing */
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#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
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#define ATA_CMD 0x07 /* command register */
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#define ATA_C_NOP 0x00 /* NOP command */
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#define ATA_C_F_FLUSHQUEUE 0x00 /* flush queued cmd's */
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#define ATA_C_F_AUTOPOLL 0x01 /* start autopoll function */
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#define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */
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#define ATA_C_READ 0x20 /* read command */
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#define ATA_C_READ48 0x24 /* read command */
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#define ATA_C_READ_DMA48 0x25 /* read w/DMA command */
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#define ATA_C_READ_DMA_QUEUED48 0x26 /* read w/DMA QUEUED command */
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#define ATA_C_READ_MUL48 0x29 /* read multi command */
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#define ATA_C_WRITE 0x30 /* write command */
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#define ATA_C_WRITE48 0x34 /* write command */
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#define ATA_C_WRITE_DMA48 0x35 /* write w/DMA command */
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#define ATA_C_WRITE_DMA_QUEUED48 0x36 /* write w/DMA QUEUED command */
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#define ATA_C_WRITE_MUL48 0x39 /* write multi command */
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#define ATA_C_PACKET_CMD 0xa0 /* packet command */
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#define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/
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#define ATA_C_SERVICE 0xa2 /* service command */
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#define ATA_C_READ_MUL 0xc4 /* read multi command */
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#define ATA_C_WRITE_MUL 0xc5 /* write multi command */
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#define ATA_C_SET_MULTI 0xc6 /* set multi size command */
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#define ATA_C_READ_DMA_QUEUED 0xc7 /* read w/DMA QUEUED command */
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#define ATA_C_READ_DMA 0xc8 /* read w/DMA command */
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#define ATA_C_WRITE_DMA 0xca /* write w/DMA command */
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#define ATA_C_WRITE_DMA_QUEUED 0xcc /* write w/DMA QUEUED command */
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#define ATA_C_SLEEP 0xe6 /* sleep command */
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#define ATA_C_FLUSHCACHE 0xe7 /* flush cache to disk */
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#define ATA_C_FLUSHCACHE48 0xea /* flush cache to disk */
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#define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */
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#define ATA_C_SETFEATURES 0xef /* features command */
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#define ATA_C_F_SETXFER 0x03 /* set transfer mode */
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#define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
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#define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */
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#define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
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#define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */
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#define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */
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#define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */
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#define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */
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#define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */
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#define ATA_STATUS 0x07 /* status register */
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#define ATA_S_ERROR 0x01 /* error */
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#define ATA_S_INDEX 0x02 /* index */
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#define ATA_S_CORR 0x04 /* data corrected */
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#define ATA_S_DRQ 0x08 /* data request */
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#define ATA_S_DSC 0x10 /* drive seek completed */
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#define ATA_S_SERVICE 0x10 /* drive needs service */
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#define ATA_S_DWF 0x20 /* drive write fault */
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#define ATA_S_DMA 0x20 /* DMA ready */
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#define ATA_S_READY 0x40 /* drive ready */
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#define ATA_S_BUSY 0x80 /* busy */
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#define ATA_ALTSTAT 0x00 /* alternate status register */
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#define ATA_ALTOFFSET 0x206 /* alternate registers offset */
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#define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */
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#define ATA_A_IDS 0x02 /* disable interrupts */
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#define ATA_A_RESET 0x04 /* RESET controller */
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#define ATA_A_4BIT 0x08 /* 4 head bits */
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/* misc defines */
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#define ATA_PRIMARY 0x1f0
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#define ATA_SECONDARY 0x170
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#define ATA_MASTER 0x00
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#define ATA_SLAVE 0x10
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#define ATA_IOSIZE 0x08
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#define ATA_ALTIOSIZE 0x01
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#define ATA_BMIOSIZE 0x08
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#define ATA_OP_FINISHED 0x00
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#define ATA_OP_CONTINUES 0x01
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#define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1)
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#define ATA_PARAM(scp, device) (scp->dev_param[ATA_DEV(device)])
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#define ATA_IOADDR_RID 0
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#define ATA_ALTADDR_RID 1
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#define ATA_BMADDR_RID 2
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#define ATA_IRQ_RID 0
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/* busmaster DMA related defines */
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#define ATA_DMA_ENTRIES 256
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#define ATA_DMA_EOT 0x80000000
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#define ATA_BMCMD_PORT 0x00
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#define ATA_BMCMD_START_STOP 0x01
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#define ATA_BMCMD_WRITE_READ 0x08
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#define ATA_BMDEVSPEC_0 0x01
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#define ATA_BMSTAT_PORT 0x02
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#define ATA_BMSTAT_ACTIVE 0x01
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#define ATA_BMSTAT_ERROR 0x02
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#define ATA_BMSTAT_INTERRUPT 0x04
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#define ATA_BMSTAT_MASK 0x07
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#define ATA_BMSTAT_DMA_MASTER 0x20
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#define ATA_BMSTAT_DMA_SLAVE 0x40
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#define ATA_BMSTAT_DMA_SIMPLEX 0x80
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#define ATA_BMDEVSPEC_1 0x03
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#define ATA_BMDTP_PORT 0x04
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/* structure for holding DMA address data */
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struct ata_dmaentry {
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u_int32_t base;
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u_int32_t count;
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};
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/* structure describing an ATA device */
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struct ata_softc {
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struct device *dev; /* device handle */
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int channel; /* channel on this controller */
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struct resource *r_io; /* io addr resource handle */
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struct resource *r_altio; /* altio addr resource handle */
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struct resource *r_bmio; /* bmio addr resource handle */
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struct resource *r_irq; /* interrupt of this channel */
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void *ih; /* interrupt handle */
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int (*intr_func)(struct ata_softc *); /* interrupt function */
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u_int32_t chiptype; /* pciid of controller chip */
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u_int32_t alignment; /* dma engine min alignment */
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char *dev_name[2]; /* name of device */
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struct ata_params *dev_param[2]; /* ptr to devices params */
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void *dev_softc[2]; /* ptr to devices softc's */
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int mode[2]; /* transfer mode for devices */
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int flags; /* controller flags */
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#define ATA_NO_SLAVE 0x01
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#define ATA_USE_16BIT 0x02
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#define ATA_ATAPI_DMA_RO 0x04
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#define ATA_QUEUED 0x08
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#define ATA_DMA_ACTIVE 0x10
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int devices; /* what is present */
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#define ATA_ATA_MASTER 0x01
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#define ATA_ATA_SLAVE 0x02
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#define ATA_ATAPI_MASTER 0x04
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#define ATA_ATAPI_SLAVE 0x08
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u_int8_t status; /* last controller status */
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u_int8_t error; /* last controller error */
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int active; /* active processing request */
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#define ATA_IDLE 0x0000
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#define ATA_IMMEDIATE 0x0001
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#define ATA_WAIT_INTR 0x0002
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#define ATA_WAIT_READY 0x0004
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#define ATA_WAIT_MASK 0x0007
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#define ATA_USE_CHS 0x0008
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#define ATA_ACTIVE 0x0010
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#define ATA_ACTIVE_ATA 0x0020
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#define ATA_ACTIVE_ATAPI 0x0040
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#define ATA_CONTROL 0x0080
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TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
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TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
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void *running; /* currently running request */
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};
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/* externs */
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extern devclass_t ata_devclass;
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/* public prototypes */
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int ata_probe(device_t);
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int ata_attach(device_t);
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int ata_detach(device_t);
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int ata_resume(device_t);
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void ata_start(struct ata_softc *);
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void ata_reset(struct ata_softc *);
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int ata_reinit(struct ata_softc *);
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int ata_wait(struct ata_softc *, int, u_int8_t);
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int ata_command(struct ata_softc *, int, u_int8_t, u_int64_t, u_int16_t, u_int8_t, int);
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int ata_printf(struct ata_softc *, int, const char *, ...) __printflike(3, 4);
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void ata_set_name(struct ata_softc *, int, char *, int);
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void ata_free_name(struct ata_softc *, int);
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int ata_get_lun(u_int32_t *);
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int ata_test_lun(u_int32_t *, int);
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void ata_free_lun(u_int32_t *, int);
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char *ata_mode2str(int);
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int ata_pmode(struct ata_params *);
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int ata_wmode(struct ata_params *);
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int ata_umode(struct ata_params *);
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int ata_find_dev(device_t, u_int32_t, u_int32_t);
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void *ata_dmaalloc(struct ata_softc *, int);
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void ata_dmainit(struct ata_softc *, int, int, int, int);
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int ata_dmasetup(struct ata_softc *, int, struct ata_dmaentry *, caddr_t, int);
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void ata_dmastart(struct ata_softc *, int, struct ata_dmaentry *, int);
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int ata_dmastatus(struct ata_softc *);
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int ata_dmadone(struct ata_softc *);
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/* macros to hide busspace uglyness */
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#define ATA_INB(res, offset) \
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bus_space_read_1(rman_get_bustag((res)), \
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rman_get_bushandle((res)), (offset))
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#define ATA_INW(res, offset) \
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bus_space_read_2(rman_get_bustag((res)), \
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rman_get_bushandle((res)), (offset))
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#define ATA_INL(res, offset) \
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bus_space_read_4(rman_get_bustag((res)), \
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rman_get_bushandle((res)), (offset))
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#define ATA_INSW(res, offset, addr, count) \
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bus_space_read_multi_2(rman_get_bustag((res)), \
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rman_get_bushandle((res)), \
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(offset), (addr), (count))
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#define ATA_INSL(res, offset, addr, count) \
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bus_space_read_multi_4(rman_get_bustag((res)), \
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rman_get_bushandle((res)), \
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(offset), (addr), (count))
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#define ATA_OUTB(res, offset, value) \
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bus_space_write_1(rman_get_bustag((res)), \
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rman_get_bushandle((res)), (offset), (value))
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#define ATA_OUTW(res, offset, value) \
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bus_space_write_2(rman_get_bustag((res)), \
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rman_get_bushandle((res)), (offset), (value))
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#define ATA_OUTL(res, offset, value) \
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bus_space_write_4(rman_get_bustag((res)), \
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rman_get_bushandle((res)), (offset), (value))
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#define ATA_OUTSW(res, offset, addr, count) \
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bus_space_write_multi_2(rman_get_bustag((res)), \
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rman_get_bushandle((res)), \
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(offset), (addr), (count))
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#define ATA_OUTSL(res, offset, addr, count) \
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bus_space_write_multi_4(rman_get_bustag((res)), \
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rman_get_bushandle((res)), \
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(offset), (addr), (count))
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