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b07d0cbce3
On modern ARM SoCs the L2 cache controller sits between the CPU and the AXI bus, and most on-chip memory-mapped devices are on the AXI bus. We map the device registers using the 'Device' memory attribute, which means the memory is not cached, but writes to it are buffered. Ensuring that a write has made it all the way to a device may require that the L2 controller take some action. There is currently only one implementation of the new function, for the PL310 cache controller. It invokes a function that the controller manual calls "cache sync" but it actually has nothing to do with cache at all, it triggers a drain of all pending store buffer writes and it blocks until they complete. The sheeva and xscale L2 controllers (which predate the concept of Device memory) don't seem to have a corresponding function. It appears that the standard armv5 drain_writebuf function includes draining all the way through the L2 controller. |
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