John Baldwin b3e9732a76 Implement a PCI interrupt router to route PCI legacy INTx interrupts to ... the legacy 8259A PICs. - Implement an ICH-comptabile PCI interrupt router on the lpc device with 8 steerable pins configured via config space access to byte-wide registers at 0x60-63 and 0x68-6b. - For each configured PCI INTx interrupt, route it to both an I/O APIC pin and a PCI interrupt router pin. When a PCI INTx interrupt is asserted, ensure that both pins are asserted. - Provide an initial routing of PCI interrupt router (PIRQ) pins to 8259A pins (ISA IRQs) and initialize the interrupt line config register for the corresponding PCI function with the ISA IRQ as this matches existing hardware. - Add a global _PIC method for OSPM to select the desired interrupt routing configuration. - Update the _PRT methods for PCI bridges to provide both APIC and legacy PRT tables and return the appropriate table based on the configured routing configuration. Note that if the lpc device is not configured, no routing information is provided. - When the lpc device is enabled, provide ACPI PCI link devices corresponding to each PIRQ pin. - Add a VMM ioctl to adjust the trigger mode (edge vs level) for 8259A pins via the ELCR. - Mark the power management SCI as level triggered. - Don't hardcode the number of elements in Packages in the source for the DSDT. iasl(8) will fill in the actual number of elements, and this makes it simpler to generate a Package with a variable number of elements. Reviewed by: tycho		2014-05-15 14:16:55 +00:00
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amd	Re-write bhyve's I/O MMU handling in terms of PCI RID.	2014-04-01 15:54:03 +00:00
intel	Ignore writes to microcode update MSR. This MSR is accessed by RHEL7 guest.	2014-04-30 02:08:27 +00:00
io	Implement a PCI interrupt router to route PCI legacy INTx interrupts to	2014-05-15 14:16:55 +00:00
vmm_dev.c	Implement a PCI interrupt router to route PCI legacy INTx interrupts to	2014-05-15 14:16:55 +00:00
vmm_host.c
vmm_host.h
vmm_instruction_emul.c	Add support for emulating the byte move and sign extend instructions:	2014-04-15 15:11:10 +00:00
vmm_ioport.c	Factor out common ioport handler code for better hygiene -- pointed	2014-04-22 16:13:56 +00:00
vmm_ioport.h	Respect the destination operand size of the 'Input from Port' instruction.	2014-04-18 15:22:56 +00:00
vmm_ipi.c
vmm_ipi.h
vmm_ktr.h
vmm_lapic.c	Local APIC access via 32-bit naturally-aligned loads is merely	2014-04-15 17:06:26 +00:00
vmm_lapic.h
vmm_mem.c
vmm_mem.h
vmm_msr.c
vmm_msr.h
vmm_stat.c
vmm_stat.h
vmm_support.S
vmm_util.c
vmm_util.h
vmm.c	Virtual machine halt detection is turned on by default. Allow it to be	2014-05-05 16:19:24 +00:00
x86.c	Account for the "plus 1" encoding of the CPUID Function 4 reported	2014-04-11 18:19:21 +00:00
x86.h