John Baldwin 3bea4efeb1 Look for capabilities in PCI-PCI bridges using the same CAP PTR register ... as for type 0 devices. Submitted by: grehan MFC after: 1 week		2006-11-16 17:31:33 +00:00
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eisa_pci.c
fixup_pci.c	Workaround a hang on some nForce2 systems that can happen if the CPU goes	2006-05-24 14:08:31 +00:00
hostb_pci.c
ignore_pci.c
isa_pci.c
pci_if.m	First cut at MI support for PCI Message Signalled Interrupts (MSI):	2006-11-13 21:47:30 +00:00
pci_pci.c	First cut at MI support for PCI Message Signalled Interrupts (MSI):	2006-11-13 21:47:30 +00:00
pci_private.h	First cut at MI support for PCI Message Signalled Interrupts (MSI):	2006-11-13 21:47:30 +00:00
pci_user.c	Actually make bounds checking for PCIOCREAD and PCIOCWRITE work.	2006-10-06 14:31:32 +00:00
pci.c	Look for capabilities in PCI-PCI bridges using the same CAP PTR register	2006-11-16 17:31:33 +00:00
pcib_if.m	First cut at MI support for PCI Message Signalled Interrupts (MSI):	2006-11-13 21:47:30 +00:00
pcib_private.h	First cut at MI support for PCI Message Signalled Interrupts (MSI):	2006-11-13 21:47:30 +00:00
pcireg.h	First cut at MI support for PCI Message Signalled Interrupts (MSI):	2006-11-13 21:47:30 +00:00
pcivar.h	Fix a couple of comment typos.	2006-11-14 17:54:55 +00:00
vga_pci.c