mirror of
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ef2ee5d07a
The following pheripherals are supported: UART, MMC, AHCI, EHCI, PCIe, I2C, PMIC, GPIO, CPU temperature and clock. Note: The PCIe driver is pure mash at this moment. It will be reworked immediately when both D5237 and D2579 enter the current tree.
481 lines
12 KiB
C
481 lines
12 KiB
C
/*-
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* Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Tegra GPIO driver.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define GPIO_LOCK_INIT(_sc) mtx_init(&_sc->sc_mtx, \
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device_get_nameunit(_sc->sc_dev), "tegra_gpio", MTX_DEF)
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#define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
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#define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
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#define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
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#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))
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#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))
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#define GPIO_BANK_OFFS 0x100 /* Bank offset */
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#define GPIO_NUM_BANKS 8 /* Total number per bank */
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#define GPIO_REGS_IN_BANK 4 /* Total registers in bank */
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#define GPIO_PINS_IN_REG 8 /* Total pin in register */
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#define GPIO_BANKNUM(n) ((n) / (GPIO_REGS_IN_BANK * GPIO_PINS_IN_REG))
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#define GPIO_PORTNUM(n) (((n) / GPIO_PINS_IN_REG) % GPIO_REGS_IN_BANK)
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#define GPIO_BIT(n) ((n) % GPIO_PINS_IN_REG)
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#define GPIO_REGNUM(n) (GPIO_BANKNUM(n) * GPIO_BANK_OFFS + \
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GPIO_PORTNUM(n) * 4)
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#define NGPIO ((GPIO_NUM_BANKS * GPIO_REGS_IN_BANK * GPIO_PINS_IN_REG) - 8)
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/* Register offsets */
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#define GPIO_CNF 0x00
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#define GPIO_OE 0x10
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#define GPIO_OUT 0x20
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#define GPIO_IN 0x30
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#define GPIO_INT_STA 0x40
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#define GPIO_INT_ENB 0x50
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#define GPIO_INT_LVL 0x60
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#define GPIO_INT_CLR 0x70
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#define GPIO_MSK_CNF 0x80
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#define GPIO_MSK_OE 0x90
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#define GPIO_MSK_OUT 0xA0
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#define GPIO_MSK_INT_STA 0xC0
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#define GPIO_MSK_INT_ENB 0xD0
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#define GPIO_MSK_INT_LVL 0xE0
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char *tegra_gpio_port_names[] = {
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"A", "B", "C", "D", /* Bank 0 */
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"E", "F", "G", "H", /* Bank 1 */
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"I", "J", "K", "L", /* Bank 2 */
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"M", "N", "O", "P", /* Bank 3 */
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"Q", "R", "S", "T", /* Bank 4 */
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"U", "V", "W", "X", /* Bank 5 */
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"Y", "Z", "AA", "BB", /* Bank 5 */
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"CC", "DD", "EE" /* Bank 5 */
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};
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struct tegra_gpio_softc {
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device_t dev;
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device_t sc_busdev;
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struct mtx sc_mtx;
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struct resource *mem_res;
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struct resource *irq_res;
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void *gpio_ih;
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int gpio_npins;
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struct gpio_pin gpio_pins[NGPIO];
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};
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static struct ofw_compat_data compat_data[] = {
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{"nvidia,tegra124-gpio", 1},
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{NULL, 0}
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};
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static inline void
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gpio_write_masked(struct tegra_gpio_softc *sc, bus_size_t reg,
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struct gpio_pin *pin, uint32_t val)
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{
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uint32_t tmp;
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int bit;
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bit = GPIO_BIT(pin->gp_pin);
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tmp = 0x100 << bit; /* mask */
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tmp |= (val & 1) << bit; /* value */
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bus_write_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin), tmp);
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}
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static inline uint32_t
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gpio_read(struct tegra_gpio_softc *sc, bus_size_t reg, struct gpio_pin *pin)
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{
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int bit;
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uint32_t val;
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bit = GPIO_BIT(pin->gp_pin);
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val = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin));
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return (val >> bit) & 1;
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}
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static void
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tegra_gpio_pin_configure(struct tegra_gpio_softc *sc, struct gpio_pin *pin,
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unsigned int flags)
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{
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if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 0)
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return;
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/* Manage input/output */
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pin->gp_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);
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if (flags & GPIO_PIN_OUTPUT) {
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pin->gp_flags |= GPIO_PIN_OUTPUT;
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gpio_write_masked(sc, GPIO_MSK_OE, pin, 1);
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} else {
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pin->gp_flags |= GPIO_PIN_INPUT;
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gpio_write_masked(sc, GPIO_MSK_OE, pin, 0);
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}
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}
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static device_t
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tegra_gpio_get_bus(device_t dev)
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{
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struct tegra_gpio_softc *sc;
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sc = device_get_softc(dev);
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return (sc->sc_busdev);
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}
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static int
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tegra_gpio_pin_max(device_t dev, int *maxpin)
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{
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*maxpin = NGPIO - 1;
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return (0);
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}
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static int
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tegra_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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{
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struct tegra_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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*caps = sc->gpio_pins[pin].gp_caps;
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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tegra_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
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{
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struct tegra_gpio_softc *sc;
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int cnf;
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sc = device_get_softc(dev);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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cnf = gpio_read(sc, GPIO_CNF, &sc->gpio_pins[pin]);
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if (cnf == 0) {
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GPIO_UNLOCK(sc);
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return (ENXIO);
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}
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*flags = sc->gpio_pins[pin].gp_flags;
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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tegra_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
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{
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struct tegra_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME);
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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tegra_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
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{
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struct tegra_gpio_softc *sc;
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int cnf;
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sc = device_get_softc(dev);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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cnf = gpio_read(sc, GPIO_CNF, &sc->gpio_pins[pin]);
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if (cnf == 0) {
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/* XXX - allow this for while ....
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GPIO_UNLOCK(sc);
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return (ENXIO);
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*/
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gpio_write_masked(sc, GPIO_MSK_CNF, &sc->gpio_pins[pin], 1);
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}
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tegra_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags);
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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tegra_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
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{
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struct tegra_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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gpio_write_masked(sc, GPIO_MSK_OUT, &sc->gpio_pins[pin], value);
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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tegra_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
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{
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struct tegra_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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*val = gpio_read(sc, GPIO_IN, &sc->gpio_pins[pin]);
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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tegra_gpio_pin_toggle(device_t dev, uint32_t pin)
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{
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struct tegra_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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gpio_write_masked(sc, GPIO_MSK_OE, &sc->gpio_pins[pin],
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gpio_read(sc, GPIO_IN, &sc->gpio_pins[pin]) ^ 1);
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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tegra_gpio_intr(void *arg)
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{
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struct tegra_gpio_softc *sc;
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uint32_t val;
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int i;
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sc = arg;
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for (i = 0; i < NGPIO; i += GPIO_PINS_IN_REG) {
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/* Clear interrupt */
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val = bus_read_4(sc->mem_res, GPIO_INT_STA + GPIO_REGNUM(i));
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val &= bus_read_4(sc->mem_res, GPIO_INT_ENB + GPIO_REGNUM(i));
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bus_write_4(sc->mem_res, GPIO_INT_CLR + GPIO_REGNUM(i), val);
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/* Interrupt handling */
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#ifdef not_yet
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for (j = 0; j < GPIO_PINS_IN_REG; j++) {
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if (val & (1 << j))
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handle_irq(i + j);
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}
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*/
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#endif
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}
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return (FILTER_HANDLED);
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}
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static int
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tegra_gpio_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
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device_set_desc(dev, "Tegra GPIO Controller");
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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tegra_gpio_detach(device_t dev)
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{
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struct tegra_gpio_softc *sc;
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sc = device_get_softc(dev);
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KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
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gpiobus_detach_bus(dev);
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if (sc->gpio_ih != NULL)
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bus_teardown_intr(dev, sc->irq_res, sc->gpio_ih);
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if (sc->irq_res != NULL)
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
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if (sc->mem_res != NULL)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
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mtx_destroy(&sc->sc_mtx);
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return(0);
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}
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static int
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tegra_gpio_attach(device_t dev)
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{
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struct tegra_gpio_softc *sc;
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int i, rid;
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sc = device_get_softc(dev);
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mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
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/* Allocate bus_space resources. */
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL) {
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device_printf(dev, "Cannot allocate memory resources\n");
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tegra_gpio_detach(dev);
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return (ENXIO);
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}
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rid = 0;
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sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
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if (sc->irq_res == NULL) {
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device_printf(dev, "Cannot allocate IRQ resources\n");
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tegra_gpio_detach(dev);
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return (ENXIO);
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}
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sc->dev = dev;
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sc->gpio_npins = NGPIO;
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if ((bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC,
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tegra_gpio_intr, NULL, sc, &sc->gpio_ih))) {
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device_printf(dev,
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"WARNING: unable to register interrupt handler\n");
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tegra_gpio_detach(dev);
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return (ENXIO);
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}
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for (i = 0; i < sc->gpio_npins; i++) {
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sc->gpio_pins[i].gp_pin = i;
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sc->gpio_pins[i].gp_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT;
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snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, "gpio_%s.%d",
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tegra_gpio_port_names[ i / GPIO_PINS_IN_REG],
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i % GPIO_PINS_IN_REG);
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sc->gpio_pins[i].gp_flags =
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gpio_read(sc, GPIO_OE, &sc->gpio_pins[i]) != 0 ?
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GPIO_PIN_OUTPUT : GPIO_PIN_INPUT;
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}
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sc->sc_busdev = gpiobus_attach_bus(dev);
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if (sc->sc_busdev == NULL) {
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tegra_gpio_detach(dev);
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return (ENXIO);
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}
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return (bus_generic_attach(dev));
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}
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static int
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tegra_map_gpios(device_t dev, phandle_t pdev, phandle_t gparent,
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int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags)
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{
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if (gcells != 2)
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return (ERANGE);
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*pin = gpios[0];
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*flags= gpios[1];
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return (0);
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}
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static phandle_t
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tegra_gpio_get_node(device_t bus, device_t dev)
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{
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/* We only have one child, the GPIO bus, which needs our own node. */
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return (ofw_bus_get_node(bus));
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}
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static device_method_t tegra_gpio_methods[] = {
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DEVMETHOD(device_probe, tegra_gpio_probe),
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DEVMETHOD(device_attach, tegra_gpio_attach),
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DEVMETHOD(device_detach, tegra_gpio_detach),
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/* GPIO protocol */
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DEVMETHOD(gpio_get_bus, tegra_gpio_get_bus),
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DEVMETHOD(gpio_pin_max, tegra_gpio_pin_max),
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DEVMETHOD(gpio_pin_getname, tegra_gpio_pin_getname),
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DEVMETHOD(gpio_pin_getflags, tegra_gpio_pin_getflags),
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DEVMETHOD(gpio_pin_getcaps, tegra_gpio_pin_getcaps),
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DEVMETHOD(gpio_pin_setflags, tegra_gpio_pin_setflags),
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DEVMETHOD(gpio_pin_get, tegra_gpio_pin_get),
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DEVMETHOD(gpio_pin_set, tegra_gpio_pin_set),
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DEVMETHOD(gpio_pin_toggle, tegra_gpio_pin_toggle),
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DEVMETHOD(gpio_map_gpios, tegra_map_gpios),
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/* ofw_bus interface */
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DEVMETHOD(ofw_bus_get_node, tegra_gpio_get_node),
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DEVMETHOD_END
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};
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static driver_t tegra_gpio_driver = {
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"gpio",
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tegra_gpio_methods,
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sizeof(struct tegra_gpio_softc),
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};
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static devclass_t tegra_gpio_devclass;
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EARLY_DRIVER_MODULE(tegra_gpio, simplebus, tegra_gpio_driver,
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tegra_gpio_devclass, 0, 0, 70);
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