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2a8c860fe3
socket-buffer implementations, introduce a return value for MCLGET() (and m_cljget() that underlies it) to allow the caller to avoid testing M_EXT itself. Update all callers to use the return value. With this change, very few network device drivers remain aware of M_EXT; the primary exceptions lie in mbuf-chain pretty printers for debugging, and in a few cases, custom mbuf and cluster allocation implementations. NB: This is a difficult-to-test change as it touches many drivers for which I don't have physical devices. Instead we've gone for intensive review, but further post-commit review would definitely be appreciated to spot errors where changes could not easily be made mechanically, but were largely mechanical in nature. Differential Revision: https://reviews.freebsd.org/D1440 Reviewed by: adrian, bz, gnn Sponsored by: EMC / Isilon Storage Division
1082 lines
27 KiB
C
1082 lines
27 KiB
C
/*-
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* Copyright (c) 1996, Javier Martín Rueda (jmrueda@diatel.upm.es)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*
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* MAINTAINER: Matthew N. Dodd <winter@jurai.net>
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* <mdodd@FreeBSD.org>
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Intel EtherExpress Pro/10, Pro/10+ Ethernet driver
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*
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* Revision history:
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*
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* dd-mmm-yyyy: Multicast support ported from NetBSD's if_iy driver.
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* 30-Oct-1996: first beta version. Inet and BPF supported, but no multicast.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/sockio.h>
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#include <sys/mbuf.h>
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#include <sys/socket.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <net/if.h>
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#include <net/if_var.h>
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#include <net/if_arp.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_types.h>
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#include <net/ethernet.h>
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#include <net/bpf.h>
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#include <netinet/in.h>
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#include <netinet/if_ether.h>
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#include <isa/isavar.h>
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#include <isa/pnpvar.h>
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#include <dev/ex/if_exreg.h>
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#include <dev/ex/if_exvar.h>
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#ifdef EXDEBUG
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# define Start_End 1
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# define Rcvd_Pkts 2
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# define Sent_Pkts 4
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# define Status 8
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static int debug_mask = 0;
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# define DODEBUG(level, action) if (level & debug_mask) action
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#else
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# define DODEBUG(level, action)
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#endif
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devclass_t ex_devclass;
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char irq2eemap[] =
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{ -1, -1, 0, 1, -1, 2, -1, -1, -1, 0, 3, 4, -1, -1, -1, -1 };
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u_char ee2irqmap[] =
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{ 9, 3, 5, 10, 11, 0, 0, 0 };
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char plus_irq2eemap[] =
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{ -1, -1, -1, 0, 1, 2, -1, 3, -1, 4, 5, 6, 7, -1, -1, -1 };
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u_char plus_ee2irqmap[] =
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{ 3, 4, 5, 7, 9, 10, 11, 12 };
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/* Network Interface Functions */
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static void ex_init(void *);
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static void ex_init_locked(struct ex_softc *);
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static void ex_start(struct ifnet *);
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static void ex_start_locked(struct ifnet *);
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static int ex_ioctl(struct ifnet *, u_long, caddr_t);
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static void ex_watchdog(void *);
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/* ifmedia Functions */
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static int ex_ifmedia_upd(struct ifnet *);
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static void ex_ifmedia_sts(struct ifnet *, struct ifmediareq *);
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static int ex_get_media(struct ex_softc *);
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static void ex_reset(struct ex_softc *);
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static void ex_setmulti(struct ex_softc *);
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static void ex_tx_intr(struct ex_softc *);
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static void ex_rx_intr(struct ex_softc *);
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void
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ex_get_address(struct ex_softc *sc, u_char *enaddr)
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{
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uint16_t eaddr_tmp;
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eaddr_tmp = ex_eeprom_read(sc, EE_Eth_Addr_Lo);
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enaddr[5] = eaddr_tmp & 0xff;
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enaddr[4] = eaddr_tmp >> 8;
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eaddr_tmp = ex_eeprom_read(sc, EE_Eth_Addr_Mid);
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enaddr[3] = eaddr_tmp & 0xff;
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enaddr[2] = eaddr_tmp >> 8;
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eaddr_tmp = ex_eeprom_read(sc, EE_Eth_Addr_Hi);
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enaddr[1] = eaddr_tmp & 0xff;
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enaddr[0] = eaddr_tmp >> 8;
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return;
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}
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int
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ex_card_type(u_char *enaddr)
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{
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if ((enaddr[0] == 0x00) && (enaddr[1] == 0xA0) && (enaddr[2] == 0xC9))
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return (CARD_TYPE_EX_10_PLUS);
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return (CARD_TYPE_EX_10);
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}
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/*
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* Caller is responsible for eventually calling
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* ex_release_resources() on failure.
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*/
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int
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ex_alloc_resources(device_t dev)
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{
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struct ex_softc * sc = device_get_softc(dev);
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int error = 0;
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sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
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&sc->ioport_rid, RF_ACTIVE);
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if (!sc->ioport) {
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device_printf(dev, "No I/O space?!\n");
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error = ENOMEM;
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goto bad;
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}
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sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
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RF_ACTIVE);
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if (!sc->irq) {
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device_printf(dev, "No IRQ?!\n");
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error = ENOMEM;
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goto bad;
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}
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bad:
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return (error);
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}
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void
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ex_release_resources(device_t dev)
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{
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struct ex_softc * sc = device_get_softc(dev);
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if (sc->ih) {
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bus_teardown_intr(dev, sc->irq, sc->ih);
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sc->ih = NULL;
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}
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if (sc->ioport) {
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bus_release_resource(dev, SYS_RES_IOPORT,
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sc->ioport_rid, sc->ioport);
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sc->ioport = NULL;
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}
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if (sc->irq) {
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bus_release_resource(dev, SYS_RES_IRQ,
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sc->irq_rid, sc->irq);
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sc->irq = NULL;
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}
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if (sc->ifp)
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if_free(sc->ifp);
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return;
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}
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int
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ex_attach(device_t dev)
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{
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struct ex_softc * sc = device_get_softc(dev);
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struct ifnet * ifp;
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struct ifmedia * ifm;
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int error;
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uint16_t temp;
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ifp = sc->ifp = if_alloc(IFT_ETHER);
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if (ifp == NULL) {
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device_printf(dev, "can not if_alloc()\n");
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return (ENOSPC);
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}
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/* work out which set of irq <-> internal tables to use */
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if (ex_card_type(sc->enaddr) == CARD_TYPE_EX_10_PLUS) {
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sc->irq2ee = plus_irq2eemap;
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sc->ee2irq = plus_ee2irqmap;
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} else {
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sc->irq2ee = irq2eemap;
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sc->ee2irq = ee2irqmap;
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}
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sc->mem_size = CARD_RAM_SIZE; /* XXX This should be read from the card itself. */
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/*
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* Initialize the ifnet structure.
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*/
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ifp->if_softc = sc;
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if_initname(ifp, device_get_name(dev), device_get_unit(dev));
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ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
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ifp->if_start = ex_start;
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ifp->if_ioctl = ex_ioctl;
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ifp->if_init = ex_init;
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IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
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ifmedia_init(&sc->ifmedia, 0, ex_ifmedia_upd, ex_ifmedia_sts);
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mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
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MTX_DEF);
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callout_init_mtx(&sc->timer, &sc->lock, 0);
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temp = ex_eeprom_read(sc, EE_W5);
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if (temp & EE_W5_PORT_TPE)
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ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
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if (temp & EE_W5_PORT_BNC)
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ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
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if (temp & EE_W5_PORT_AUI)
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ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
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ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
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ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_NONE, 0, NULL);
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ifmedia_set(&sc->ifmedia, ex_get_media(sc));
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ifm = &sc->ifmedia;
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ifm->ifm_media = ifm->ifm_cur->ifm_media;
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ex_ifmedia_upd(ifp);
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/*
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* Attach the interface.
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*/
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ether_ifattach(ifp, sc->enaddr);
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error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
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NULL, ex_intr, (void *)sc, &sc->ih);
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if (error) {
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device_printf(dev, "bus_setup_intr() failed!\n");
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ether_ifdetach(ifp);
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mtx_destroy(&sc->lock);
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return (error);
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}
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return(0);
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}
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int
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ex_detach(device_t dev)
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{
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struct ex_softc *sc;
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struct ifnet *ifp;
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sc = device_get_softc(dev);
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ifp = sc->ifp;
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EX_LOCK(sc);
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ex_stop(sc);
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EX_UNLOCK(sc);
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ether_ifdetach(ifp);
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callout_drain(&sc->timer);
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ex_release_resources(dev);
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mtx_destroy(&sc->lock);
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return (0);
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}
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static void
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ex_init(void *xsc)
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{
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struct ex_softc * sc = (struct ex_softc *) xsc;
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EX_LOCK(sc);
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ex_init_locked(sc);
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EX_UNLOCK(sc);
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}
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static void
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ex_init_locked(struct ex_softc *sc)
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{
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struct ifnet * ifp = sc->ifp;
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int i;
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unsigned short temp_reg;
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DODEBUG(Start_End, printf("%s: ex_init: start\n", ifp->if_xname););
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sc->tx_timeout = 0;
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/*
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* Load the ethernet address into the card.
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*/
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CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
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temp_reg = CSR_READ_1(sc, EEPROM_REG);
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if (temp_reg & Trnoff_Enable)
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CSR_WRITE_1(sc, EEPROM_REG, temp_reg & ~Trnoff_Enable);
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for (i = 0; i < ETHER_ADDR_LEN; i++)
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CSR_WRITE_1(sc, I_ADDR_REG0 + i, IF_LLADDR(sc->ifp)[i]);
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/*
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* - Setup transmit chaining and discard bad received frames.
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* - Match broadcast.
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* - Clear test mode.
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* - Set receiving mode.
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*/
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CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | Tx_Chn_Int_Md | Tx_Chn_ErStp | Disc_Bad_Fr);
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CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | No_SA_Ins | RX_CRC_InMem);
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CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3) & 0x3f /* XXX constants. */ );
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/*
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* - Set IRQ number, if this part has it. ISA devices have this,
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* while PC Card devices don't seem to. Either way, we have to
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* switch to Bank1 as the rest of this code relies on that.
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*/
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CSR_WRITE_1(sc, CMD_REG, Bank1_Sel);
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if (sc->flags & HAS_INT_NO_REG)
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CSR_WRITE_1(sc, INT_NO_REG,
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(CSR_READ_1(sc, INT_NO_REG) & 0xf8) |
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sc->irq2ee[sc->irq_no]);
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/*
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* Divide the available memory in the card into rcv and xmt buffers.
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* By default, I use the first 3/4 of the memory for the rcv buffer,
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* and the remaining 1/4 of the memory for the xmt buffer.
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*/
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sc->rx_mem_size = sc->mem_size * 3 / 4;
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sc->tx_mem_size = sc->mem_size - sc->rx_mem_size;
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sc->rx_lower_limit = 0x0000;
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sc->rx_upper_limit = sc->rx_mem_size - 2;
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sc->tx_lower_limit = sc->rx_mem_size;
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sc->tx_upper_limit = sc->mem_size - 2;
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CSR_WRITE_1(sc, RCV_LOWER_LIMIT_REG, sc->rx_lower_limit >> 8);
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CSR_WRITE_1(sc, RCV_UPPER_LIMIT_REG, sc->rx_upper_limit >> 8);
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CSR_WRITE_1(sc, XMT_LOWER_LIMIT_REG, sc->tx_lower_limit >> 8);
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CSR_WRITE_1(sc, XMT_UPPER_LIMIT_REG, sc->tx_upper_limit >> 8);
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/*
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* Enable receive and transmit interrupts, and clear any pending int.
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*/
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CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | TriST_INT);
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CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
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CSR_WRITE_1(sc, MASK_REG, All_Int & ~(Rx_Int | Tx_Int));
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CSR_WRITE_1(sc, STATUS_REG, All_Int);
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/*
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* Initialize receive and transmit ring buffers.
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*/
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CSR_WRITE_2(sc, RCV_BAR, sc->rx_lower_limit);
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sc->rx_head = sc->rx_lower_limit;
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CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit | 0xfe);
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CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit);
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sc->tx_head = sc->tx_tail = sc->tx_lower_limit;
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ifp->if_drv_flags |= IFF_DRV_RUNNING;
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ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
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DODEBUG(Status, printf("OIDLE init\n"););
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callout_reset(&sc->timer, hz, ex_watchdog, sc);
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ex_setmulti(sc);
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|
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/*
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* Final reset of the board, and enable operation.
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*/
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CSR_WRITE_1(sc, CMD_REG, Sel_Reset_CMD);
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DELAY(2);
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CSR_WRITE_1(sc, CMD_REG, Rcv_Enable_CMD);
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ex_start_locked(ifp);
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DODEBUG(Start_End, printf("%s: ex_init: finish\n", ifp->if_xname););
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}
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|
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static void
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ex_start(struct ifnet *ifp)
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{
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struct ex_softc * sc = ifp->if_softc;
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EX_LOCK(sc);
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ex_start_locked(ifp);
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EX_UNLOCK(sc);
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}
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|
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static void
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ex_start_locked(struct ifnet *ifp)
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{
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struct ex_softc * sc = ifp->if_softc;
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int i, len, data_len, avail, dest, next;
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unsigned char tmp16[2];
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struct mbuf * opkt;
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struct mbuf * m;
|
|
|
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DODEBUG(Start_End, printf("ex_start%d: start\n", unit););
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|
|
|
/*
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|
* Main loop: send outgoing packets to network card until there are no
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|
* more packets left, or the card cannot accept any more yet.
|
|
*/
|
|
while (((opkt = ifp->if_snd.ifq_head) != NULL) &&
|
|
!(ifp->if_drv_flags & IFF_DRV_OACTIVE)) {
|
|
|
|
/*
|
|
* Ensure there is enough free transmit buffer space for
|
|
* this packet, including its header. Note: the header
|
|
* cannot wrap around the end of the transmit buffer and
|
|
* must be kept together, so we allow space for twice the
|
|
* length of the header, just in case.
|
|
*/
|
|
|
|
for (len = 0, m = opkt; m != NULL; m = m->m_next) {
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len += m->m_len;
|
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}
|
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|
|
data_len = len;
|
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|
|
DODEBUG(Sent_Pkts, printf("1. Sending packet with %d data bytes. ", data_len););
|
|
|
|
if (len & 1) {
|
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len += XMT_HEADER_LEN + 1;
|
|
} else {
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|
len += XMT_HEADER_LEN;
|
|
}
|
|
|
|
if ((i = sc->tx_tail - sc->tx_head) >= 0) {
|
|
avail = sc->tx_mem_size - i;
|
|
} else {
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|
avail = -i;
|
|
}
|
|
|
|
DODEBUG(Sent_Pkts, printf("i=%d, avail=%d\n", i, avail););
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|
|
|
if (avail >= len + XMT_HEADER_LEN) {
|
|
IF_DEQUEUE(&ifp->if_snd, opkt);
|
|
|
|
#ifdef EX_PSA_INTR
|
|
/*
|
|
* Disable rx and tx interrupts, to avoid corruption
|
|
* of the host address register by interrupt service
|
|
* routines.
|
|
* XXX Is this necessary with splimp() enabled?
|
|
*/
|
|
CSR_WRITE_1(sc, MASK_REG, All_Int);
|
|
#endif
|
|
|
|
/*
|
|
* Compute the start and end addresses of this
|
|
* frame in the tx buffer.
|
|
*/
|
|
dest = sc->tx_tail;
|
|
next = dest + len;
|
|
|
|
if (next > sc->tx_upper_limit) {
|
|
if ((sc->tx_upper_limit + 2 - sc->tx_tail) <=
|
|
XMT_HEADER_LEN) {
|
|
dest = sc->tx_lower_limit;
|
|
next = dest + len;
|
|
} else {
|
|
next = sc->tx_lower_limit +
|
|
next - sc->tx_upper_limit - 2;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Build the packet frame in the card's ring buffer.
|
|
*/
|
|
DODEBUG(Sent_Pkts, printf("2. dest=%d, next=%d. ", dest, next););
|
|
|
|
CSR_WRITE_2(sc, HOST_ADDR_REG, dest);
|
|
CSR_WRITE_2(sc, IO_PORT_REG, Transmit_CMD);
|
|
CSR_WRITE_2(sc, IO_PORT_REG, 0);
|
|
CSR_WRITE_2(sc, IO_PORT_REG, next);
|
|
CSR_WRITE_2(sc, IO_PORT_REG, data_len);
|
|
|
|
/*
|
|
* Output the packet data to the card. Ensure all
|
|
* transfers are 16-bit wide, even if individual
|
|
* mbufs have odd length.
|
|
*/
|
|
for (m = opkt, i = 0; m != NULL; m = m->m_next) {
|
|
DODEBUG(Sent_Pkts, printf("[%d]", m->m_len););
|
|
if (i) {
|
|
tmp16[1] = *(mtod(m, caddr_t));
|
|
CSR_WRITE_MULTI_2(sc, IO_PORT_REG,
|
|
(uint16_t *) tmp16, 1);
|
|
}
|
|
CSR_WRITE_MULTI_2(sc, IO_PORT_REG,
|
|
(uint16_t *) (mtod(m, caddr_t) + i),
|
|
(m->m_len - i) / 2);
|
|
if ((i = (m->m_len - i) & 1) != 0) {
|
|
tmp16[0] = *(mtod(m, caddr_t) +
|
|
m->m_len - 1);
|
|
}
|
|
}
|
|
if (i)
|
|
CSR_WRITE_MULTI_2(sc, IO_PORT_REG,
|
|
(uint16_t *) tmp16, 1);
|
|
/*
|
|
* If there were other frames chained, update the
|
|
* chain in the last one.
|
|
*/
|
|
if (sc->tx_head != sc->tx_tail) {
|
|
if (sc->tx_tail != dest) {
|
|
CSR_WRITE_2(sc, HOST_ADDR_REG,
|
|
sc->tx_last + XMT_Chain_Point);
|
|
CSR_WRITE_2(sc, IO_PORT_REG, dest);
|
|
}
|
|
CSR_WRITE_2(sc, HOST_ADDR_REG,
|
|
sc->tx_last + XMT_Byte_Count);
|
|
i = CSR_READ_2(sc, IO_PORT_REG);
|
|
CSR_WRITE_2(sc, HOST_ADDR_REG,
|
|
sc->tx_last + XMT_Byte_Count);
|
|
CSR_WRITE_2(sc, IO_PORT_REG, i | Ch_bit);
|
|
}
|
|
|
|
/*
|
|
* Resume normal operation of the card:
|
|
* - Make a dummy read to flush the DRAM write
|
|
* pipeline.
|
|
* - Enable receive and transmit interrupts.
|
|
* - Send Transmit or Resume_XMT command, as
|
|
* appropriate.
|
|
*/
|
|
CSR_READ_2(sc, IO_PORT_REG);
|
|
#ifdef EX_PSA_INTR
|
|
CSR_WRITE_1(sc, MASK_REG, All_Int & ~(Rx_Int | Tx_Int));
|
|
#endif
|
|
if (sc->tx_head == sc->tx_tail) {
|
|
CSR_WRITE_2(sc, XMT_BAR, dest);
|
|
CSR_WRITE_1(sc, CMD_REG, Transmit_CMD);
|
|
sc->tx_head = dest;
|
|
DODEBUG(Sent_Pkts, printf("Transmit\n"););
|
|
} else {
|
|
CSR_WRITE_1(sc, CMD_REG, Resume_XMT_List_CMD);
|
|
DODEBUG(Sent_Pkts, printf("Resume\n"););
|
|
}
|
|
|
|
sc->tx_last = dest;
|
|
sc->tx_tail = next;
|
|
|
|
BPF_MTAP(ifp, opkt);
|
|
|
|
sc->tx_timeout = 2;
|
|
if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
|
|
m_freem(opkt);
|
|
} else {
|
|
ifp->if_drv_flags |= IFF_DRV_OACTIVE;
|
|
DODEBUG(Status, printf("OACTIVE start\n"););
|
|
}
|
|
}
|
|
|
|
DODEBUG(Start_End, printf("ex_start%d: finish\n", unit););
|
|
}
|
|
|
|
void
|
|
ex_stop(struct ex_softc *sc)
|
|
{
|
|
|
|
DODEBUG(Start_End, printf("ex_stop%d: start\n", unit););
|
|
|
|
EX_ASSERT_LOCKED(sc);
|
|
/*
|
|
* Disable card operation:
|
|
* - Disable the interrupt line.
|
|
* - Flush transmission and disable reception.
|
|
* - Mask and clear all interrupts.
|
|
* - Reset the 82595.
|
|
*/
|
|
CSR_WRITE_1(sc, CMD_REG, Bank1_Sel);
|
|
CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) & ~TriST_INT);
|
|
CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
|
|
CSR_WRITE_1(sc, CMD_REG, Rcv_Stop);
|
|
sc->tx_head = sc->tx_tail = sc->tx_lower_limit;
|
|
sc->tx_last = 0; /* XXX I think these two lines are not necessary, because ex_init will always be called again to reinit the interface. */
|
|
CSR_WRITE_1(sc, MASK_REG, All_Int);
|
|
CSR_WRITE_1(sc, STATUS_REG, All_Int);
|
|
CSR_WRITE_1(sc, CMD_REG, Reset_CMD);
|
|
DELAY(200);
|
|
sc->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
|
|
sc->tx_timeout = 0;
|
|
callout_stop(&sc->timer);
|
|
|
|
DODEBUG(Start_End, printf("ex_stop%d: finish\n", unit););
|
|
|
|
return;
|
|
}
|
|
|
|
void
|
|
ex_intr(void *arg)
|
|
{
|
|
struct ex_softc *sc = (struct ex_softc *)arg;
|
|
struct ifnet *ifp = sc->ifp;
|
|
int int_status, send_pkts;
|
|
int loops = 100;
|
|
|
|
DODEBUG(Start_End, printf("ex_intr%d: start\n", unit););
|
|
|
|
EX_LOCK(sc);
|
|
send_pkts = 0;
|
|
while (loops-- > 0 &&
|
|
(int_status = CSR_READ_1(sc, STATUS_REG)) & (Tx_Int | Rx_Int)) {
|
|
/* don't loop forever */
|
|
if (int_status == 0xff)
|
|
break;
|
|
if (int_status & Rx_Int) {
|
|
CSR_WRITE_1(sc, STATUS_REG, Rx_Int);
|
|
ex_rx_intr(sc);
|
|
} else if (int_status & Tx_Int) {
|
|
CSR_WRITE_1(sc, STATUS_REG, Tx_Int);
|
|
ex_tx_intr(sc);
|
|
send_pkts = 1;
|
|
}
|
|
}
|
|
if (loops == 0)
|
|
printf("100 loops are not enough\n");
|
|
|
|
/*
|
|
* If any packet has been transmitted, and there are queued packets to
|
|
* be sent, attempt to send more packets to the network card.
|
|
*/
|
|
if (send_pkts && (ifp->if_snd.ifq_head != NULL))
|
|
ex_start_locked(ifp);
|
|
EX_UNLOCK(sc);
|
|
|
|
DODEBUG(Start_End, printf("ex_intr%d: finish\n", unit););
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
ex_tx_intr(struct ex_softc *sc)
|
|
{
|
|
struct ifnet * ifp = sc->ifp;
|
|
int tx_status;
|
|
|
|
DODEBUG(Start_End, printf("ex_tx_intr%d: start\n", unit););
|
|
|
|
/*
|
|
* - Cancel the watchdog.
|
|
* For all packets transmitted since last transmit interrupt:
|
|
* - Advance chain pointer to next queued packet.
|
|
* - Update statistics.
|
|
*/
|
|
|
|
sc->tx_timeout = 0;
|
|
|
|
while (sc->tx_head != sc->tx_tail) {
|
|
CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_head);
|
|
|
|
if (!(CSR_READ_2(sc, IO_PORT_REG) & Done_bit))
|
|
break;
|
|
|
|
tx_status = CSR_READ_2(sc, IO_PORT_REG);
|
|
sc->tx_head = CSR_READ_2(sc, IO_PORT_REG);
|
|
|
|
if (tx_status & TX_OK_bit) {
|
|
if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
|
|
} else {
|
|
if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
|
|
}
|
|
|
|
if_inc_counter(ifp, IFCOUNTER_COLLISIONS, tx_status & No_Collisions_bits);
|
|
}
|
|
|
|
/*
|
|
* The card should be ready to accept more packets now.
|
|
*/
|
|
|
|
ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
|
|
|
|
DODEBUG(Status, printf("OIDLE tx_intr\n"););
|
|
DODEBUG(Start_End, printf("ex_tx_intr%d: finish\n", unit););
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
ex_rx_intr(struct ex_softc *sc)
|
|
{
|
|
struct ifnet * ifp = sc->ifp;
|
|
int rx_status;
|
|
int pkt_len;
|
|
int QQQ;
|
|
struct mbuf * m;
|
|
struct mbuf * ipkt;
|
|
struct ether_header * eh;
|
|
|
|
DODEBUG(Start_End, printf("ex_rx_intr%d: start\n", unit););
|
|
|
|
/*
|
|
* For all packets received since last receive interrupt:
|
|
* - If packet ok, read it into a new mbuf and queue it to interface,
|
|
* updating statistics.
|
|
* - If packet bad, just discard it, and update statistics.
|
|
* Finally, advance receive stop limit in card's memory to new location.
|
|
*/
|
|
|
|
CSR_WRITE_2(sc, HOST_ADDR_REG, sc->rx_head);
|
|
|
|
while (CSR_READ_2(sc, IO_PORT_REG) == RCV_Done) {
|
|
|
|
rx_status = CSR_READ_2(sc, IO_PORT_REG);
|
|
sc->rx_head = CSR_READ_2(sc, IO_PORT_REG);
|
|
QQQ = pkt_len = CSR_READ_2(sc, IO_PORT_REG);
|
|
|
|
if (rx_status & RCV_OK_bit) {
|
|
MGETHDR(m, M_NOWAIT, MT_DATA);
|
|
ipkt = m;
|
|
if (ipkt == NULL) {
|
|
if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
|
|
} else {
|
|
ipkt->m_pkthdr.rcvif = ifp;
|
|
ipkt->m_pkthdr.len = pkt_len;
|
|
ipkt->m_len = MHLEN;
|
|
|
|
while (pkt_len > 0) {
|
|
if (pkt_len >= MINCLSIZE) {
|
|
if (MCLGET(m, M_NOWAIT)) {
|
|
m->m_len = MCLBYTES;
|
|
} else {
|
|
m_freem(ipkt);
|
|
if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
|
|
goto rx_another;
|
|
}
|
|
}
|
|
m->m_len = min(m->m_len, pkt_len);
|
|
|
|
/*
|
|
* NOTE: I'm assuming that all mbufs allocated are of even length,
|
|
* except for the last one in an odd-length packet.
|
|
*/
|
|
|
|
CSR_READ_MULTI_2(sc, IO_PORT_REG,
|
|
mtod(m, uint16_t *), m->m_len / 2);
|
|
|
|
if (m->m_len & 1) {
|
|
*(mtod(m, caddr_t) + m->m_len - 1) = CSR_READ_1(sc, IO_PORT_REG);
|
|
}
|
|
pkt_len -= m->m_len;
|
|
|
|
if (pkt_len > 0) {
|
|
MGET(m->m_next, M_NOWAIT, MT_DATA);
|
|
if (m->m_next == NULL) {
|
|
m_freem(ipkt);
|
|
if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
|
|
goto rx_another;
|
|
}
|
|
m = m->m_next;
|
|
m->m_len = MLEN;
|
|
}
|
|
}
|
|
eh = mtod(ipkt, struct ether_header *);
|
|
#ifdef EXDEBUG
|
|
if (debug_mask & Rcvd_Pkts) {
|
|
if ((eh->ether_dhost[5] != 0xff) || (eh->ether_dhost[0] != 0xff)) {
|
|
printf("Receive packet with %d data bytes: %6D -> ", QQQ, eh->ether_shost, ":");
|
|
printf("%6D\n", eh->ether_dhost, ":");
|
|
} /* QQQ */
|
|
}
|
|
#endif
|
|
EX_UNLOCK(sc);
|
|
(*ifp->if_input)(ifp, ipkt);
|
|
EX_LOCK(sc);
|
|
if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
|
|
}
|
|
} else {
|
|
if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
|
|
}
|
|
CSR_WRITE_2(sc, HOST_ADDR_REG, sc->rx_head);
|
|
rx_another: ;
|
|
}
|
|
|
|
if (sc->rx_head < sc->rx_lower_limit + 2)
|
|
CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit);
|
|
else
|
|
CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_head - 2);
|
|
|
|
DODEBUG(Start_End, printf("ex_rx_intr%d: finish\n", unit););
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
static int
|
|
ex_ioctl(register struct ifnet *ifp, u_long cmd, caddr_t data)
|
|
{
|
|
struct ex_softc * sc = ifp->if_softc;
|
|
struct ifreq * ifr = (struct ifreq *)data;
|
|
int error = 0;
|
|
|
|
DODEBUG(Start_End, printf("%s: ex_ioctl: start ", ifp->if_xname););
|
|
|
|
switch(cmd) {
|
|
case SIOCSIFADDR:
|
|
case SIOCGIFADDR:
|
|
case SIOCSIFMTU:
|
|
error = ether_ioctl(ifp, cmd, data);
|
|
break;
|
|
|
|
case SIOCSIFFLAGS:
|
|
DODEBUG(Start_End, printf("SIOCSIFFLAGS"););
|
|
EX_LOCK(sc);
|
|
if ((ifp->if_flags & IFF_UP) == 0 &&
|
|
(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
|
|
ex_stop(sc);
|
|
} else {
|
|
ex_init_locked(sc);
|
|
}
|
|
EX_UNLOCK(sc);
|
|
break;
|
|
case SIOCADDMULTI:
|
|
case SIOCDELMULTI:
|
|
ex_init(sc);
|
|
error = 0;
|
|
break;
|
|
case SIOCSIFMEDIA:
|
|
case SIOCGIFMEDIA:
|
|
error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, cmd);
|
|
break;
|
|
default:
|
|
DODEBUG(Start_End, printf("unknown"););
|
|
error = EINVAL;
|
|
}
|
|
|
|
DODEBUG(Start_End, printf("\n%s: ex_ioctl: finish\n", ifp->if_xname););
|
|
|
|
return(error);
|
|
}
|
|
|
|
static void
|
|
ex_setmulti(struct ex_softc *sc)
|
|
{
|
|
struct ifnet *ifp;
|
|
struct ifmultiaddr *maddr;
|
|
uint16_t *addr;
|
|
int count;
|
|
int timeout, status;
|
|
|
|
ifp = sc->ifp;
|
|
|
|
count = 0;
|
|
if_maddr_rlock(ifp);
|
|
TAILQ_FOREACH(maddr, &ifp->if_multiaddrs, ifma_link) {
|
|
if (maddr->ifma_addr->sa_family != AF_LINK)
|
|
continue;
|
|
count++;
|
|
}
|
|
if_maddr_runlock(ifp);
|
|
|
|
if ((ifp->if_flags & IFF_PROMISC) || (ifp->if_flags & IFF_ALLMULTI)
|
|
|| count > 63) {
|
|
/* Interface is in promiscuous mode or there are too many
|
|
* multicast addresses for the card to handle */
|
|
CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
|
|
CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | Promisc_Mode);
|
|
CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));
|
|
CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
|
|
}
|
|
else if ((ifp->if_flags & IFF_MULTICAST) && (count > 0)) {
|
|
/* Program multicast addresses plus our MAC address
|
|
* into the filter */
|
|
CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
|
|
CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | Multi_IA);
|
|
CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));
|
|
CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
|
|
|
|
/* Borrow space from TX buffer; this should be safe
|
|
* as this is only called from ex_init */
|
|
|
|
CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_lower_limit);
|
|
CSR_WRITE_2(sc, IO_PORT_REG, MC_Setup_CMD);
|
|
CSR_WRITE_2(sc, IO_PORT_REG, 0);
|
|
CSR_WRITE_2(sc, IO_PORT_REG, 0);
|
|
CSR_WRITE_2(sc, IO_PORT_REG, (count + 1) * 6);
|
|
|
|
if_maddr_rlock(ifp);
|
|
TAILQ_FOREACH(maddr, &ifp->if_multiaddrs, ifma_link) {
|
|
if (maddr->ifma_addr->sa_family != AF_LINK)
|
|
continue;
|
|
|
|
addr = (uint16_t*)LLADDR((struct sockaddr_dl *)
|
|
maddr->ifma_addr);
|
|
CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
|
|
CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
|
|
CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
|
|
}
|
|
if_maddr_runlock(ifp);
|
|
|
|
/* Program our MAC address as well */
|
|
/* XXX: Is this necessary? The Linux driver does this
|
|
* but the NetBSD driver does not */
|
|
addr = (uint16_t*)IF_LLADDR(sc->ifp);
|
|
CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
|
|
CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
|
|
CSR_WRITE_2(sc, IO_PORT_REG, *addr++);
|
|
|
|
CSR_READ_2(sc, IO_PORT_REG);
|
|
CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit);
|
|
CSR_WRITE_1(sc, CMD_REG, MC_Setup_CMD);
|
|
|
|
sc->tx_head = sc->tx_lower_limit;
|
|
sc->tx_tail = sc->tx_head + XMT_HEADER_LEN + (count + 1) * 6;
|
|
|
|
for (timeout=0; timeout<100; timeout++) {
|
|
DELAY(2);
|
|
if ((CSR_READ_1(sc, STATUS_REG) & Exec_Int) == 0)
|
|
continue;
|
|
|
|
status = CSR_READ_1(sc, CMD_REG);
|
|
CSR_WRITE_1(sc, STATUS_REG, Exec_Int);
|
|
break;
|
|
}
|
|
|
|
sc->tx_head = sc->tx_tail;
|
|
}
|
|
else
|
|
{
|
|
/* No multicast or promiscuous mode */
|
|
CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
|
|
CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) & 0xDE);
|
|
/* ~(Multi_IA | Promisc_Mode) */
|
|
CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3));
|
|
CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
|
|
}
|
|
}
|
|
|
|
static void
|
|
ex_reset(struct ex_softc *sc)
|
|
{
|
|
|
|
DODEBUG(Start_End, printf("ex_reset%d: start\n", unit););
|
|
|
|
EX_ASSERT_LOCKED(sc);
|
|
ex_stop(sc);
|
|
ex_init_locked(sc);
|
|
|
|
DODEBUG(Start_End, printf("ex_reset%d: finish\n", unit););
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
ex_watchdog(void *arg)
|
|
{
|
|
struct ex_softc * sc = arg;
|
|
struct ifnet *ifp = sc->ifp;
|
|
|
|
if (sc->tx_timeout && --sc->tx_timeout == 0) {
|
|
DODEBUG(Start_End, if_printf(ifp, "ex_watchdog: start\n"););
|
|
|
|
ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
|
|
|
|
DODEBUG(Status, printf("OIDLE watchdog\n"););
|
|
|
|
if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
|
|
ex_reset(sc);
|
|
ex_start_locked(ifp);
|
|
|
|
DODEBUG(Start_End, if_printf(ifp, "ex_watchdog: finish\n"););
|
|
}
|
|
|
|
callout_reset(&sc->timer, hz, ex_watchdog, sc);
|
|
}
|
|
|
|
static int
|
|
ex_get_media(struct ex_softc *sc)
|
|
{
|
|
int current;
|
|
int media;
|
|
|
|
media = ex_eeprom_read(sc, EE_W5);
|
|
|
|
CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
|
|
current = CSR_READ_1(sc, REG3);
|
|
CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
|
|
|
|
if ((current & TPE_bit) && (media & EE_W5_PORT_TPE))
|
|
return(IFM_ETHER|IFM_10_T);
|
|
if ((current & BNC_bit) && (media & EE_W5_PORT_BNC))
|
|
return(IFM_ETHER|IFM_10_2);
|
|
|
|
if (media & EE_W5_PORT_AUI)
|
|
return (IFM_ETHER|IFM_10_5);
|
|
|
|
return (IFM_ETHER|IFM_AUTO);
|
|
}
|
|
|
|
static int
|
|
ex_ifmedia_upd(ifp)
|
|
struct ifnet * ifp;
|
|
{
|
|
struct ex_softc * sc = ifp->if_softc;
|
|
|
|
if (IFM_TYPE(sc->ifmedia.ifm_media) != IFM_ETHER)
|
|
return EINVAL;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
ex_ifmedia_sts(ifp, ifmr)
|
|
struct ifnet * ifp;
|
|
struct ifmediareq * ifmr;
|
|
{
|
|
struct ex_softc * sc = ifp->if_softc;
|
|
|
|
EX_LOCK(sc);
|
|
ifmr->ifm_active = ex_get_media(sc);
|
|
ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
|
|
EX_UNLOCK(sc);
|
|
|
|
return;
|
|
}
|
|
|
|
u_short
|
|
ex_eeprom_read(struct ex_softc *sc, int location)
|
|
{
|
|
int i;
|
|
u_short data = 0;
|
|
int read_cmd = location | EE_READ_CMD;
|
|
short ctrl_val = EECS;
|
|
|
|
CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
|
|
CSR_WRITE_1(sc, EEPROM_REG, EECS);
|
|
for (i = 8; i >= 0; i--) {
|
|
short outval = (read_cmd & (1 << i)) ? ctrl_val | EEDI : ctrl_val;
|
|
CSR_WRITE_1(sc, EEPROM_REG, outval);
|
|
CSR_WRITE_1(sc, EEPROM_REG, outval | EESK);
|
|
DELAY(3);
|
|
CSR_WRITE_1(sc, EEPROM_REG, outval);
|
|
DELAY(2);
|
|
}
|
|
CSR_WRITE_1(sc, EEPROM_REG, ctrl_val);
|
|
|
|
for (i = 16; i > 0; i--) {
|
|
CSR_WRITE_1(sc, EEPROM_REG, ctrl_val | EESK);
|
|
DELAY(3);
|
|
data = (data << 1) |
|
|
((CSR_READ_1(sc, EEPROM_REG) & EEDO) ? 1 : 0);
|
|
CSR_WRITE_1(sc, EEPROM_REG, ctrl_val);
|
|
DELAY(2);
|
|
}
|
|
|
|
ctrl_val &= ~EECS;
|
|
CSR_WRITE_1(sc, EEPROM_REG, ctrl_val | EESK);
|
|
DELAY(3);
|
|
CSR_WRITE_1(sc, EEPROM_REG, ctrl_val);
|
|
DELAY(2);
|
|
CSR_WRITE_1(sc, CMD_REG, Bank0_Sel);
|
|
return(data);
|
|
}
|